Canon Kabushiki Kaisha

Takayuki Kamiya

Ayaka Kinoshita

An image processing device includes: an integrated circuit chip arranged on a substrate to perform processing on image data; a first memory chip arranged adjacent to the integrated circuit chip on the substrate and connected to the integrated circuit chip; and a second memory chip stacked on the integrated circuit chip and connected to the integrated circuit chip, wherein the integrated circuit chip sets, according to the processing content, any one of a plurality of operation modes including a first operation mode to operate the first memory chip and limit operation of the second memory chip, and a second operation mode to operate the first memory chip and the second memory chip.

Image processing device having an integrated circuit chip, a first memory chip and a second memory chip, and control method therefor

An integrated circuit device comprises N stacked first integrated circuit chips each of which includes a first circuit and N stacked second integrated circuit chips each of which includes a second circuit. The N stacked second integrated circuit chips are stacked on the N stacked first integrated circuit chips. A first and second integrated circuit chips at symmetric positions with respect to a reference surface are paired. Each of the first and second integrated circuit chips include connection terminals for connecting the first circuit of the first integrated circuit chip and the second circuit of the second integrated circuit chip in the pair, and through electrodes each penetrating an inside of the chip. The connection terminals and through electrodes are arranged to be symmetric with respect to the reference surface.

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Kunitachi, Japan

Takayuki Kamiya