Yamaha Corporation

Takayuki Kamiya

Masayoshi Omura

Kunihiko Mitsuoka

A method of manufacturing a CMOS-BJT semiconductor device comprises the steps of: forming a collector region of a first conductivity type and a first well of the first conductivity type, simultaneously in a semiconductor substrate; forming a second well of a second conductivity type opposite to said first conductivity type, in the semiconductor substrate; forming a base region of the second conductivity type in the collector region; forming first and second insulated gate structure on said first and second wells, and a junction protection structure having same constituent elements as said insulated gate structures on said base region; and forming second source/drain regions of the first conductivity type in said second well, and an emitter region of the first conductivity type in the base region, simultaneously, with an emitter-base junction reaching the principal surface below said junction protection structure.

Semiconductor device including bipolar junction transistor with protected emitter-base junction

A semiconductor device has: a fuse having one end applied with a first voltage, and a MOS transistor having source, gate and drain and a connection point between the other end of the fuse and one of the source and drain, a second voltage lower than the first voltage applied to the other of the source and drain, wherein: the first and second voltages, characteristics of the MOS transistor and a resistance of the fuse are selected so that the fuse can be broken down when a predetermined program voltage is applied to the gate; and the resistance of the fuse is set to such a value as a voltage difference between a voltage at the connection point and the second voltage is lower than a drain voltage of the MOS transistor at which a drain current starts saturating, when the program voltage is applied to the gate.

Semiconductor device having fuse and its manufacture method

Method of breaking down a fuse in a semiconductor device

A method of fabricating a multi power source semiconductor device handling multi-level voltages, comprises the steps of: forming first gate oxide layers by thermally oxidizing surfaces of the plurality of the active regions of said semiconductor substrate; forming a first mask having a window on a first active region among said plurality of the active regions of said semiconductor substrate; implanting impurity ions for controlling a threshold voltage, into a surface of said first active region through the first mask; removing the first gate oxide layer on the first active region exposed in the window of said first mask; removing said first mask; forming a thin second gate oxide layer on the first active region and a thick third gate oxide layer on a second active region different from the first active region among said plurality of the active regions by further thermally oxidizing the surfaces of the plurality of the active regions; forming on the semiconductor substrate a second mask having a window on the second active region; and implanting impurity ions for controlling a threshold voltage, into a surface of the second active region through said second mask. A method of fabricating a multi power source semiconductor device capable of realizing gate oxide layers of different thickness and different channel doping with a small number of masks is provided.

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Hamamatsu, Japan

Takayuki Kamiya