Semiconductor Energy Laboratory Co., Ltd.

Takayuki Ikeda

Yoshiyuki Kurokawa

Shunpei Yamazaki

Munehiro Kozuma

Takeshi Aoki

Hikaru Tamura

Takashi Nakagawa

Hidetomo Kobayashi

Yuki Okamoto

Kiyotaka Kimura

Kei Takahashi

Daisuke Kawae

Hitoshi Kunitake

Masataka Ikeda

Masami Endo

Jun Koyama

Hajime Kimura

Hideaki Shishido

Takayuki Inoue

Naoto Kusumoto

Takanori Matsuzaki

Hiroki Inoue

Takeya Hirose

Shuichi Katsui

Takeshi Osada

Ryota Tajima

Seiichi Yoneda

Yutaka Shionoiri

Tomoaki Atsumi

Takahiko Ishizu

Kiyoshi Kato

Takeshi Fukunaga

Atsuo Isobe

Masato Ishii

Takahiro Fukutome

Yusuke Negoro

Hiroki Dembo

Koji Kusunoki

Atsushi Miyaguchi

Yuto Yakubo

Kosei Nei

Roh Yamamoto

Shintaro Harada

Shingo Eguchi

Tatsuya Onuki

Koji Dairiki

Yuta Endo

Yu Yamazaki

Hiroshi Shibata

Hidehito Kitakado

Mayumi Mikami

Junpei Sugao

Tatsunori Inoue

Hidekazu Miyairi

Yoshiaki Oikawa

Hiromichi Godo

Takashi Hamada

Yohei Momma

Satoshi Kobayashi

Akio Suzuki

Kazuko Yamawaki

Yasuhiko Takemura

Hiroyuki Miyake

Akihisa Shimomura

Kosei Noda

Kouhei Toyotaka

Tetsuji Ishitani

Kensuke Yoshizumi

Shuhei Nagatsuka

Kazutaka Kuriki

Konami Izumi

Toshiyuki Isa

Tetsuya Kakehata

Yuichi Yanagisawa

Ryo Tokumaru

Kazuaki Ohshima

Seiko Inoue

Shuji Fukai

Haruyuki Baba

Kentaro Hayashi

Kazuma Furutani

Naoaki Tsutsui

Kazuki Tsuda

Minato Ito

Seiya Saito

Yuki Tamatsukuri

Yurika Sato

Shota Mizukami

Noriko Harima

Shoki Miyata

Noriko Matsumoto

A computer system with a small circuit area and reduced power consumption is used. The computer system includes a computer node including a processor and a three-dimensional NAND memory device. The three-dimensional NAND memory device includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell. Thus, the computer node can eliminate a main memory such as a DRAM from the structure.

Computer system using 3D OS NAND

A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

Memory device and electronic device

A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.

Display device and electronic device

A novel display device is provided. The display device includes a plurality of pixels each including a light-emitting device, a sensor device, a first circuit device, and a second circuit device. The light-emitting device and the sensor device are provided in a first layer. The first circuit device is provided in a second layer. The second circuit device is provided in a third layer. The light-emitting device includes a lower electrode, an upper electrode, and a light-emitting layer provided between the lower electrode and the upper electrode. The sensor device has a function of detecting light emitted from the light-emitting device. The first circuit device has a function of driving the light-emitting device or the sensor device. The second circuit device has a function of performing an arithmetic operation based on information output from the first circuit device. The first layer is provided over the second layer. The second layer is provided over the third layer.

Display device with light emitting device and light sensing device in one layer

A battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including either of the battery circuits are provided. The power storage device includes a first circuit portion, a second circuit portion, a third circuit portion, and a secondary battery; the first circuit portion has a function of controlling charging of the secondary battery; the first circuit portion has a function of supplying the start time and the end time of the charging of the secondary battery to the third circuit portion; the second circuit portion has functions of generating a first voltage and a first current and supplying them to the third circuit portion; the third circuit portion has a function of generating a second voltage by charging the first current in a capacitor; and the third circuit portion has a function of comparing the first voltage and the second voltage.

Power storage device and method for operating power storage device

A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.

Semiconductor device

A semiconductor device with a novel structure is provided. The semiconductor device includes a memory circuit including a first transistor and a second transistor. The first transistor is formed on a silicon substrate. The second transistor is formed in a layer above a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode with a first channel formation region interposed therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate. The second transistor includes a second channel formation region. The second channel formation region includes a metal oxide.

A novel semiconductor device that is highly convenient or reliable is provided. The semiconductor device includes a sensor unit, a first memory unit, a second memory unit, and a determination unit. The sensor unit supplies a sensor signal, the first memory unit retains the sensor signal, the second memory unit retains standard data and allowable difference information, the determination unit compares the sensor signal with the standard data, and the determination unit supplies a control signal in the case where a difference between the sensor signal and the standard data exceeds the allowable difference information.

Semiconductor device sensor unit

A novel display apparatus that is highly convenient, useful, or reliable is provided. The display apparatus includes a first pixel set, a second pixel set, a first conductive film, and a second conductive film; the first pixel set includes a first light-emitting device set and a first pixel circuit set; the first pixel circuit set includes a first group of pixel circuits; and the first group of pixel circuits include a first pixel circuit. The second pixel set includes a second light-emitting device set and a second pixel circuit set; the second light-emitting device set is electrically connected to the second pixel circuit set; the second pixel circuit set includes a second group of pixel circuits; and the second group of pixel circuits include a second pixel circuit. The first conductive film is electrically connected to the first group of pixel circuits and the second group of pixel circuits, and the second conductive film is electrically connected to the first pixel circuit and the second pixel circuit.

Display apparatus having pixel sets including light-emitting devices

A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

A semiconductor device with low power consumption is provided. In a cascode circuit including a first transistor provided on a low power supply potential side and a second transistor provided on a high power supply potential side, a source or a drain of a third transistor and a capacitor are connected to a gate of the second transistor. A gate of the first transistor is electrically connected to a back gate of the second transistor. An OS transistor is used as the third transistor.

Semiconductor device and electronic device

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Semiconductor device and manufacturing method thereof

An imaging device suitable for detecting infrared light is provided. The imaging device includes a first layer, a second layer, a third layer, and a fourth layer, which are stacked in this order. The first layer includes an infrared-light-transmitting filter. The second layer includes single crystal silicon. The third layer includes a device-formation layer. The fourth layer includes a support substrate. The second layer includes a photoelectric-conversion device whose light-absorption layer is the single crystal silicon. The third layer includes a transistor which includes a metal oxide in its channel formation region. The photoelectric-conversion device and the transistor are electrically connected. The photoelectric-conversion device receives light which has passed through the infrared-light-transmitting filter.

Imaging device, manufacturing method thereof, and electronic device

A display device with high design flexibility that can be designed easily is provided. One embodiment of the present invention includes a first substrate () provided with a driver circuit including first and second pulse output circuits (__), a second substrate () provided with a display unit () including a first pixel circuit including a first source wiring (SL_) and a first contact portion (SC_) and a second pixel circuit including a second source wiring (SL_) adjacent to the first source wiring and a second contact portion (SC_) electrically connected to the second source wiring, and a connection unit where the first and second substrates are electrically connected to each other. The display unit is placed to overlap with the driver circuit, the first and second pulse output circuits are electrically connected to the first and second pixel circuits respectively through the first and second contact portions, the first pulse output circuit is placed on an opposite side of a straight line connecting the first and second contact portions from the second pulse output circuit, and the connection unit includes a wiring containing copper.

Display device with a driver circuit comprising a plurality of pulse output circuits

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Kanagawa, Japan

Takayuki Ikeda