Semiconductor Energy Laboratory Co., Ltd.

Takayuki Ikeda

Yoshiyuki Kurokawa

Shunpei Yamazaki

Munehiro Kozuma

Takeshi Aoki

Hikaru Tamura

Takashi Nakagawa

Hidetomo Kobayashi

Yuki Okamoto

Daisuke Kawae

Kiyotaka Kimura

Kei Takahashi

Hitoshi Kunitake

Masataka Ikeda

Masami Endo

Jun Koyama

Hajime Kimura

Takayuki Inoue

Naoto Kusumoto

Hideaki Shishido

Takeya Hirose

Shuichi Katsui

Takeshi Osada

Seiichi Yoneda

Yutaka Shionoiri

Takanori Matsuzaki

Tomoaki Atsumi

Hiroki Inoue

Kiyoshi Kato

Takeshi Fukunaga

Atsuo Isobe

Ryota Tajima

Masato Ishii

Hiroki Dembo

Yusuke Negoro

Koji Kusunoki

Takahiko Ishizu

Takahiro Fukutome

Yuto Yakubo

Roh Yamamoto

Shintaro Harada

Shingo Eguchi

Tatsuya Onuki

Koji Dairiki

Yuta Endo

Yu Yamazaki

Hiroshi Shibata

Atsushi Miyaguchi

Hidehito Kitakado

Kosei Nei

Junpei Sugao

Tatsunori Inoue

Hidekazu Miyairi

Yoshiaki Oikawa

Hiromichi Godo

Takashi Hamada

Mayumi Mikami

Satoshi Kobayashi

Akio Suzuki

Kazuko Yamawaki

Yasuhiko Takemura

Hiroyuki Miyake

Akihisa Shimomura

Kosei Noda

Kouhei Toyotaka

Tetsuji Ishitani

Kensuke Yoshizumi

Shuhei Nagatsuka

Konami Izumi

Toshiyuki Isa

Tetsuya Kakehata

Yohei Momma

Yuichi Yanagisawa

Ryo Tokumaru

Kazuaki Ohshima

Seiko Inoue

Shuji Fukai

Haruyuki Baba

Kentaro Hayashi

Naoaki Tsutsui

Kazuki Tsuda

Minato Ito

Yuki Tamatsukuri

Yurika Sato

Seiya Saito

Shota Mizukami

Noriko Harima

Shoki Miyata

Noriko Matsumoto

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

Display device and electronic device

A semiconductor device with low power consumption is provided. In a cascode circuit including a first transistor provided on a low power supply potential side and a second transistor provided on a high power supply potential side, a source or a drain of a third transistor and a capacitor are connected to a gate of the second transistor. A gate of the first transistor is electrically connected to a back gate of the second transistor. An OS transistor is used as the third transistor.

Semiconductor device and electronic device

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Semiconductor device and manufacturing method thereof

An imaging device suitable for detecting infrared light is provided. The imaging device includes a first layer, a second layer, a third layer, and a fourth layer, which are stacked in this order. The first layer includes an infrared-light-transmitting filter. The second layer includes single crystal silicon. The third layer includes a device-formation layer. The fourth layer includes a support substrate. The second layer includes a photoelectric-conversion device whose light-absorption layer is the single crystal silicon. The third layer includes a transistor which includes a metal oxide in its channel formation region. The photoelectric-conversion device and the transistor are electrically connected. The photoelectric-conversion device receives light which has passed through the infrared-light-transmitting filter.

Imaging device, manufacturing method thereof, and electronic device

A display device with high design flexibility that can be designed easily is provided. One embodiment of the present invention includes a first substrate () provided with a driver circuit including first and second pulse output circuits (__), a second substrate () provided with a display unit () including a first pixel circuit including a first source wiring (SL_) and a first contact portion (SC_) and a second pixel circuit including a second source wiring (SL_) adjacent to the first source wiring and a second contact portion (SC_) electrically connected to the second source wiring, and a connection unit where the first and second substrates are electrically connected to each other. The display unit is placed to overlap with the driver circuit, the first and second pulse output circuits are electrically connected to the first and second pixel circuits respectively through the first and second contact portions, the first pulse output circuit is placed on an opposite side of a straight line connecting the first and second contact portions from the second pulse output circuit, and the connection unit includes a wiring containing copper.

Display device with a driver circuit comprising a plurality of pulse output circuits

A semiconductor device includes a switch, a capacitor, a chopping circuit, and an amplifier. The amplifier includes a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal. The semiconductor device, with use of the switch and the capacitor, has a function of sampling and holding a first potential and a second potential input in a first period. The chopping circuit is provided on each of the input terminal side and the output terminal side of the amplifier, and the first potential and the second potential are each input to either one of the non-inverting input terminal and the inverting input terminal in a second period. In a third period, the first potential and the second potential are each input to either one of the non-inverting input terminal and the inverting input terminal, which is different from the second period.

Semiconductor device and operation method thereof

An imaging device having a memory function is provided. Alternatively, an imaging device suitable for taking images of a moving object is provided. The imaging device includes first to third layers; the second layer is provided between the first and the third layer; the first layer includes a photoelectric conversion device; the second layer includes a first and a second circuit; the third layer includes a third and a fourth circuit; the first circuit and the photoelectric conversion device have a function of generating imaging data; the third circuit has a function of reading the imaging data; the second circuit has a function of storing the imaging data read by the third circuit; the fourth circuit has a function of reading the imaging data stored in the second circuit; and the first circuit and the second circuit include a transistor including a metal oxide in a channel formation region.

Imaging device and electronic device

A communication device that can transmit and receive a signal with a large amplitude is provided. The communication device includes an amplifier circuit including first to fourth transistors, first to fourth bias transistors, first to fourth loads, and first to fourth terminals. The drains of the first to fourth transistors are electrically connected to the sources of the first to fourth bias transistors. The sources of the first to fourth transistors are electrically connected to power supply lines. The gates of the first and second bias transistors are electrically connected to a first wiring, and the gates of the third and fourth bias transistors are electrically connected to a second wiring. The first to fourth terminals are electrically connected to the gates of the first to fourth transistors, the drains of the third, fourth, first, and second bias transistors, and the first to fourth loads.

Communication device

One embodiment of the present invention is a display device including a first insulating layer, a second insulating layer, a first transistor, a second transistor, a first light-emitting diode, a second light-emitting diode, and a color conversion layer. The first insulating layer is over the first transistor and the second transistor. The first light-emitting diode and the second light-emitting diode are over the first insulating layer. The color conversion layer is over the second light-emitting diode. The color conversion layer is configured to convert light emitted from the second light-emitting diode into a light having a longer wavelength. The first transistor and the second transistor each include a metal oxide layer and a gate electrode. The metal oxide layer includes a channel formation region. A top surface of the gate electrode is level or substantially level with a top surface of the second insulating layer.

Display device, display module, electronic device, and manufacturing method of display device

A display device with a novel structure is provided. The display device includes a first substrate provided with a plurality of pixels including a display element, and a second substrate including a first conductive layer provided with a plurality of first openings. The first conductive layer has a function of an antenna capable of transmitting and receiving a radio signal. The pixel and the first opening include a region where the pixel and the first opening overlap with each other. The second substrate includes an element layer. The element layer includes a transistor. The transistor has a function of an amplifier capable of amplifying the radio signal. The transistor each includes a semiconductor layer including a metal oxide in a channel formation region. The metal oxide contains In, Ga, and Zn.

Display device

A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.

Semiconductor device, battery pack, and electronic device

The safety is ensured in such a manner that an abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early and a warning is given to a user. A first protection circuit and a second protection circuit are provided for one secondary battery. The first protection circuit includes a memory circuit including a transistor including an oxide semiconductor. Combination of a plurality of protection circuits enables a complementary double protection system in charging, and the safety can be further enhanced.

Protection circuit for secondary battery and abnormality detection system of secondary battery

An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.

A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

Memory device, operation method of memory device, data processing device, data processing system, and electronic device

An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

Arithmetic device and electronic device

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Kanagawa, Japan

Takayuki Ikeda