Renesas Electronics Corporation

Other

Mitsubishi Denki Kabushiki Kaisha

Mitsumi Electric Company Ltd.

Ryoden Semiconductor System Engineering Corporation

Takayuki Igarashi

Takuo Funaya

Ken'ichi Furukawa

Yoshitaka Ohtsu

Yoshitaka Ootsu

Hirokazu Sayama

Tetsuya Nitta

Kakutaro Suda

Tomohiko Aika

Takehiro Ochi

Yoshikazu Tsunemine

Toshihiko Yasuma

A semiconductor device including an element isolation in a trench formed in an upper surface of a semiconductor substrate, a trench isolation including a void in a trench directly under the element isolation, and a Cu wire with Cu ball connected to a pad on the semiconductor substrate, is formed. The semiconductor device has a circular trench isolation arrangement prohibition region that overlaps the end portion of the Cu ball in plan view, and the trench isolation is separated from the trench isolation arrangement prohibition region in plan view.

Semiconductor device

Reliability of a semiconductor device is improved. The semiconductor device includes a silicon pattern for a fuse element, a metal silicide layer formed on an upper surface and a side surface of the silicon pattern, a gate electrode for MISFET, and a metal silicide layer formed on an upper surface of the gate electrode. The height from the lower surface of the silicon pattern to the lower end of the metal silicide layer is lower than the height from the lower surface of the gate electrode to the lower end of the metal silicide layer.

Semiconductor device and method of manufacturing the same

Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CLand a wiring Mformed on an interlayer insulator IL, a wiring Mformed on an interlayer insulator IL, and a coil CLand a wiring Mformed on the interlayer insulator IL. Moreover, a distance DMbetween the coil CLand the wiring Mis longer than a distance DMbetween the coil CLand the wiring M(DM&#x3e;DM). Furthermore, the distance DMbetween the coil CLand the wiring Mis set to be longer than a sum of a film thickness of the interlayer insulator ILand a film thickness of the interlayer insulator IL, which are positioned between the coil CLand the coil CL. In this manner, it is possible to improve an insulation withstand voltage between the coil CLand the wiring Mor the like, where a high voltage difference tend to occur. Moreover, a transformer formation regionA and a seal ring formation regionC surrounding a peripheral circuit formation regionB are formed so as to improve the moisture resistance.

Semiconductor device with coils in different wiring layers

A semiconductor device including: a semiconductor substrate; a first coil formed on the semiconductor substrate via a first insulation film; a second insulation film formed on the semiconductor substrate so as to cover the first insulation film and the first coil; a first pad formed on the second insulation film and disposed at a position not overlapped with the first coil in a planar view; a laminated insulation film formed on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; a second coil formed on the laminated insulation film and disposed above the first coil; and a first wiring formed on the laminated insulation film including an upper portion of the first pad exposed from the first opening, the first wiring being electrically connected to the first pad.

Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CLand a wiring Mformed on an interlayer insulator IL, a wiring Mformed on an interlayer insulator IL, and a coil CLand a wiring Mformed on the interlayer insulator IL. Moreover, a distance DMbetween the coil CLand the wiring Mis longer than a distance DMbetween the coil CLand the wiring M(DMDM). Furthermore, the distance DMbetween the coil CLand the wiring Mis set to be longer than a sum of a film thickness of the interlayer insulator ILand a film thickness of the interlayer insulator IL, which are positioned between the coil CLand the coil CL. In this manner, it is possible to improve an insulation withstand voltage between the coil CLand the wiring Mor the like, where a high voltage difference tend to occur. Moreover, a transformer formation regionA and a seal ring formation regionC surrounding a peripheral circuit formation regionB are formed so as to improve the moisture resistance.

Semiconductor device with inductively coupled coils

A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a manufacturing method thereof are provided. A discontinued part, in which the interface between an interlayer insulating film and a passivation film is discontinued, is formed between a first wiring layer and a second wiring layer that are adjacent to each other with a space therebetween. Both the interlayer insulating film and the passivation film face an air gap in the discontinued part.

Semiconductor device having a discontinued part between a first insulating film and a second insulating film

A method of manufacturing a semiconductor device including: (a) forming a first insulation film on a semiconductor substrate; (b) forming a first coil on the first insulation film; (c) forming a second insulation film on the first insulation film so as to cover the first coil; (d) forming a first pad on the second insulation film at a position not overlapped with the first coil in a planar view; (e) forming a laminated insulation film on the second insulation film, the laminated insulation film having a first opening from which the first pad is exposed; and (f) forming a second coil and a first wiring on the laminated insulation film, wherein the second coil is disposed above the first coil, the first coil and the second coil are not connected by a conductor but magnetically coupled to each other, the first wiring is formed from an upper portion of the first pad to an upper portion of the laminated insulation film and is electrically connected to the first pad, and the laminated insulation film includes a silicon oxide film, a silicon nitride film on the silicon oxide film, and a resin film on the silicon nitride film.

A coil CLis formed on a semiconductor substrate SB via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil CL, and a pad PDis formed on the second insulation film. A laminated film LF having an opening OPfrom which the pad PDis partially exposed is formed on the second insulation film, and a coil CLis formed on the laminated insulation film. The coil CLis disposed above the coil CL, and the coil CLand the coil CLare magnetically coupled to each other. The laminated film LF is composed of a silicon oxide film LF, a silicon nitride film LFthereon, and a resin film LFthereon.

Provided is a semiconductor device having improved reliability. Over a semiconductor substrate, a first coil is formed via a first insulating film. A second insulating film is formed so as to cover the first insulating film and the first coil. Over the second insulating film, a pad is formed. Over the second insulating film, a multi-layer film having an opening exposing a part of the pad is formed. Over the multi-layer insulating film, a second coil is formed. The second coil is placed over the first coil. The second and first coils are magnetically coupled to each other. The multi-layer film includes a silicon dioxide film, a silicon nitride film over the silicon dioxide film, and a resin film over the silicon nitride film.

Method of manufacturing semiconductor device

A polysilicon film that serves as a resistance element is formed. The polysilicon film is patterned to a predetermined shape. CVD oxide films covering the patterned polysilicon film are etched thereby removing the portion of the CVD oxide film where the contact region is formed, leaving the portion covering the portion of the polysilicon film that serves as the resistor main body. BFis implanted by using the portions of the remaining CVD oxide films covering the polysilicon film as an implantation mask thereby forming a high concentration region in the contact region.

An N-layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N-layer, a trench isolation region is formed to surround the N-layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N-layer. Between trench isolation region and the N-layer, a P type diffusion regionis formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N-layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

Semiconductor device and manufacturing method thereof

In a capacitor formation area A , a capacitor C is formed. The capacitor is constituted by a lower-layer electrode-use polysilicon layer (lower-layer electrode) formed on a LOCOS separation film , a nitride film (dielectric film) and an upper-layer electrode-use polysilicon layer (upper-layer electrode). In this case, the lower-layer electrode-use polysilicon layer and the nitride film are formed as the same plane pattern. In CMOS formation area A , an NMOS transistor Q is formed on a P-well region and a PMOS transistor Q is formed in an N-well region . Both of the gate electrodes of NMOS transistor Q and NMOS transistor Q are formed by the upper-layer electrode-use polysilicon layer

Manufacturing method of semiconductor device

A collector region is formed on a semiconductor substrate. An emitter electrode, an external base electrode and a gate electrode are formed on the semiconductor substrate. The position of the interface between the gate electrode and the semiconductor substrate is rendered higher than the position of the interface between the external base electrode and the semiconductor substrate. Thus provided is a semiconductor device so improved that dispersion of the withstand voltage of a gate oxide film and dispersion of characteristics such as a threshold voltage and a drain-to-source current are reduced.

Semiconductor device and method of fabricating the same

A structure of a BiCMOS transistor hindering over-etching of source/drain regions of a MOS transistor and a manufacturing method thereof are provided. A polysilicon film that is to be a gate electrode lower layer of a MOS transistor is formed, and thereon, another polysilicon film that is to be a gate electrode upper layer of the MOS transistor as well as to be a base electrode of a bipolar transistor is formed. Thereafter, etching is conducted to form the polysilicon film to be the base electrode of the bipolar transistor and the gate electrode at the same time. Here, an oxide film shown in FIG. 4 serves as a protective film, thereby hindering over-etching of n type and p type wells to be active regions of respective MOS transistors.

Growing community of inventors

Tokyo, Japan

Takayuki Igarashi