Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Takayuki Hirose

Norihito Tsukahara

Toshiyuki Kojima

Kohichi Tanda

Keiko Ikuta

Manabu Gokan

Tsukasa Shiraishi

Akihisa Nakahashi

Yasushi Taniguchi

Seiji Kumazawa

Tsuneyuki Ejima

Masayoshi Koyama

Takayuki Ashida

Yoko Kasai

Lianji Jin

A highly reliable joined structure and joining method by suppressing peeling at joined portions in the joined structure formed by joining metals together is provided. A joined structure includes a plurality of metals laminated and joined together. The plurality of metals are shaped to include a plurality of convex portions arranged on a surface positioned in a lamination direction, and flat portions arranged between the plural convex portions. Tip ends of the plurality of convex portions are formed as curved surfaces.

Joined structure and joining method

A semiconductor device () includes: a semiconductor chip () having a first main surface and a second main surface opposite to the first main surface; a heat dissipating plate () opposed to the first main surface; a first electrode () disposed between the first main surface and the heat dissipating plate () so as to be electrically connected to the semiconductor chip (); a pressure contact member () opposed to the second main surface; a second electrode () disposed between the second main surface and the pressure contact member () so as to be electrically connected to the semiconductor chip (); and a pressure generating mechanism that generates a pressure for pressing the first electrode () into contact with the heat dissipating plate () and the semiconductor chip () and pressing the second electrode () into contact with the pressure contact member () and the semiconductor chip ().

Semiconductor device and method for manufacturing the same

A pressed-contact type semiconductor device includes a power semiconductor element, on an upper surface of which at least a first electrode is formed and on a lower surface of which at least a second electrode is formed, lead frames which face the first electrode and the second electrode of the power semiconductor element respectively, and a clip which applies a pressure to the lead frames while the power semiconductor element is sandwiched by the lead frames, wherein a metallic porous plating part is formed on a surface which faces the first electrode or the second electrode, the surface being a surface of at least one of the lead frames.

Pressed-contact type semiconductor device and method for manufacturing the same

A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

Semiconductor device having a porous nickel plating part

A wiring board is provided that suppresses spreading of liquid droplets when liquid droplets are discharged using an ink-jet method. The wiring board has a plurality of layers and includes an ink-jet wiring pattern that is formed in a soluble porous membrane member of any single layer and that includes electrically conductive nanoparticles as a principal material, and a transferred wiring pattern that does not include electrically conductive nanoparticles as a principal material. One layer among the plurality of layers is an electrically insulative substrate. Another layer among the plurality of layers is a porous membrane treated member layer including a porous membrane member at one part of a region of the other layer. The ink-jet wiring pattern is formed in the porous membrane treated member layer. The transferred wiring pattern is formed in the substrate.

Wiring board and wiring board manufacturing method

Provided is a layered electronic circuit device capable of realizing high-density/high-function mounting, easily inspecting and repairing the respective constituent elements, and improving the electronic connection characteristic. The layered electronic circuit device includes a first circuit substrate () and a second circuit substrate () which are arranged in parallel such that their substrate surfaces are opposed to each other. The peripheral portion of the first circuit substrate () and the peripheral portion of the second circuit substrate () are connected to each other by connection members (to) having a wiring member () and a thermal hardening anisotropic conductive sheet (), thereby performing electric connection.

Layered electronic circuit device

Ink having the optimum contact angle relative to a partition wall is selected for forming a pixel, based on the relationship with an inclination angle of the partition wall. The ink applied to the opening of the partition wall is dried to form the pixel such that an outer edge in contact with the partition wall has a thickness of at least 35% of the maximum height of the partition wall and a difference between the maximum thickness and the average thickness and a difference between the minimum thickness and the average thickness are not larger than 35% of the average thickness in an effective pixel area.

Growing community of inventors

Osaka, Japan

Takayuki Hirose