Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Kabsuhiki Kaisha Toshiba

Takayuki Hiraoka

Ichiro Mizushima

Yoshitaka Tsunashima

Kiyotaka Miyano

Yasushi Akasaka

Tsunetoshi Arikado

Kyoichi Suguro

Kentaro Watanabe

Koichi Sato

Naoyuki Shigyo

Toshikazu Fukuda

Tsutomu Kojima

Atsushi Honjoh

Kenji Honda

Kyoioni Suguro

Kuniaki Utsumi

According to one embodiment, an electrostatic protection circuit includes first, second and third diodes, a resistance element, and a MOS field-effect transistor. The first diode is coupled to a first wiring. The second diode is coupled between the first diode and a second wiring. The third diode is coupled between the first wiring and a first node at which the first diode and the second diode are coupled to each other. The resistance element is coupled between the third diode and the first wiring. The MOS field-effect transistor is coupled between the first node and the first wiring. A gate of the MOS field-effect transistor is electrically coupled to a second node at which the resistance element and the third diode are coupled to each other.

Electrostatic protection circuit

A semiconductor device includes an I/O circuit configured to be supplied with a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage, and to receive an input signal based on the first voltage. The I/O circuit includes an enabler circuit configured to be supplied with the second voltage, and to generate a first signal based on the second voltage, and a first level shifter circuit coupled to the enabler circuit, and configured to, based on the first signal, level-shift a signal based on the second voltage to a signal based on the third voltage.

Semiconductor device

A Schmitt trigger circuit includes a first circuit; a second circuit; a first switch; a third circuit; and a second switch. The first circuit output the output signal of a second or first logical level. The second circuit is coupled to a first potential node at a first end, and sends a current between the first end and a second end based on the output signal. The first switch electrically couples or uncouples the second end and a first node based on a selection signal. The third circuit is coupled to a second potential node at a third end, and sends a current exclusively with the second circuit between the third end and a fourth end based on the output signal. The second switch electrically couples or uncouples the fourth end and the first node based on the selection signal.

Schmitt trigger circuit

A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.

Semiconductor device having non-silicide region in which no silicide is formed on diffusion layer

A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

Semiconductor device having an element isolating insulating film

An electrostatic protection circuit including: a first power supply terminal; a second power supply terminal; an input-output terminalfor an external connection; a P-type MOSFET for a bufferfor pulling up input and output to a high-level potential; an N-type MOSFET for the bufferfor pulling down the input and output to a low-level potential; a rectifying elementconnected between the first and second power supply terminals; a detectorfor comparing the potential of the input-output terminalto the potential of the first power supply terminalto detect whether or not an electrostatic surge is flowing in; and controllersand, wherein the controllersandcontrol a gate potential of the N-type MOSFETfor the buffer when the detectordetects inflow of the electrostatic surge and turn off the N-type MOSFETfor the buffer. Discharge of the electrostatic surge is performed through a parasitic bipolar junction transistorformed on the N-type MOSFET

A semiconductor device includes a protection circuit protecting a semiconductor integrated circuit from electrostatic discharge, the protection circuit has a detection circuit detecting the electrostatic discharge, a trigger circuit generating a trigger signal based on the output signal of the detection circuit, and a thyristor having a PNP transistor and an NPN transistor, and operating by the trigger signal from the trigger circuit, the PNP transistor having an emitter connected to a first terminal of the semiconductor device, the NPN transistor having an emitter connected to a second terminal of the semiconductor device and a collector connected to base of the PNP transistor. The protection circuit further has a switching element controlling the connected between the PNP and NPN transistors in accordance with the output signal of the detection circuit.

Semiconductor device including a protection circuit

In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.

Semiconductor device and method for manufacturing

There is disclosed a semiconductor device comprising at least one first pad being formed above a substrate and given a first potential, at least one first conductive layer being formed between the first pad and the substrate so as to be electrically connected to the first pad, at least one second pad being formed above the substrate so as to sandwich the at least one first conductive layer between the second pad and the substrate, and given a second potential different from the first potential, at least one second conductive layer being formed between the first and second pads and the substrate so as to be electrically connected to the second pad, and a plurality of insulating layers being stacked on the substrate and at least one of the insulating layers being as an inter-electrode insulator of a capacitance element.

Growing community of inventors

Kawasaki, Japan

Takayuki Hiraoka