Kabushiki Kaisha Toshiba

Takayuki Harima

Kenichi Nakamura

Makoto Segawa

Yoshihiko Kamata

Yasuhiko Honda

Masami Masuda

Takao Nakajima

Mitsugi Ogura

Yoshikazu Takeyama

Yasushi Kameda

Hiroshi Takamoto

Takahiro Tsuruto

A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit.

Semiconductor memory

A first circuit is disposed on the semiconductor substrate, operates synchronously with a first clock signal, and outputs a first output signal delayed by a first delay time from the first clock signal. A first measuring circuit measures indirectly a first increase and a first decrease of the first delay time. A setting circuit operates synchronously with the first clock signal, outputs a second clock signal delayed from the first clock signal by a second delay time adding the first increase and subtracting the first decrease. A second circuit inputs the first output signal and operates synchronously with the second clock signal.

Semiconductor device having a first clock signal configured to operate sychronously with a second clock signal by use of a measuring and setting circuit

A semiconductor memory device includes a memory cell array, an address register for taking in an address synchronizing with a clock, a decode circuit for selecting a memory cell of the memory cell array by decoding the address retained in the address register, a reading/writing circuit for reading data from the memory cell array and writing the data to the memory cell array, a data register for temporarily retaining the data read from and written to the memory cell array, synchronizing with the clock, and an echo signal generation circuit, synchronizing with the clock, for outputting an echo signal composed of a predetermined expected value pattern for notifying the outside of a data output with a delay time equal to a transmission delay time of the output data read from the memory cell array.

Semiconductor memory device having an echo signal generating circuit

A semiconductor memory device according to the present invention includes a burst counter for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subsequent operation cycle in accordance with the inputted initial address, and a plurality of memory cell sub-arrays which is formed by dividing a memory cell array. The semiconductor memory device further comprises a plurality of block decoder selection-time adjusting circuits for sequentially outputting a first block selecting signal, which is the base of a signal for selecting each of the memory cell sub-arrays, as a second block selecting signal at a timing corresponding to a read latency and for outputting the first block selecting signal as a third block selecting signal which has a length corresponding to the read latency.

Semiconductor memory device

An input buffer circuit is connected to a first power supply voltage pad for applying a first power supply voltage, and a first ground line. An internal circuit larger in power consumption than the input buffer circuit is connected to a second power supply voltage pad for applying a second power supply voltage, and a second ground line. The parasitic resistance of the first ground line is higher than that of the second ground line. By connecting a capacitance between a power supply line connected to the first power supply voltage pad, and the first ground line, fluctuations in first power supply voltage are suppressed to prevent the input buffer circuit from malfunctioning.

Semiconductor device having improved immunity to power supply voltage

A semiconductor device which achieves high-speed access and prevents the latch-up for any power inputting sequence by a plurality of power sources is disclosed. Where the chip voltage VDD is earlier inputted, an N well bias circuit 9 and a P well bias circuit 10 are activated, and an N-type well 12 and a P-type well 13 are biased respectively. After that, although the interface voltage VDDQ is inputted, the latch-up is not generated. On the other hand, where the interface voltage VDDQ is earlier inputted to a terminal 8, the N well bias circuit 9 and the P well bias circuit 10 are activated through a bypass circuit 15, and the N-type well 12 and the P-type well 13 are biased. Accordingly, although the chip voltage VDD is inputted after that, the latch-up is not generated.

Semiconductor device

A semiconductor device comprises: a memory cell array which has a plurality of memory cell to output data from a memory cell selected on the basis of an externally input signal; a sense amplifier for receiving the data output from said memory cell array, amplifying the data, and outputting the data; and a pulse generator for receiving the input signal and outputting a pulse for determining a timing at which said sense amplifier is activated, wherein said pulse generator includes a circuit pattern electrically equivalent to elements included in said memory cell. According to the above device, the pulse generator includes the same pattern as that of elements included in the memory cell. When the operation speed of the memory cell varies due to the manufacturing process, etc, the variation can be canceled by a similar variation, so that an erroneous operation of the sense amplifier is prevented and the operation speed can be increased.

A semiconductor memory device includes memory cell array blocks and row spare cell groups provided for the memory cell array blocks adjacent to each other and each of the row spare cell groups having a plurality of spare cells for relieving defective memory cells in the adjacent memory cell array blocks. The row spare cell groups are shared by the plurality of adjacent memory cell array blocks, hence the spare cells are allocated corresponding to the defective cells found in the memory cell array blocks, thus enhancing a relieving rate by a redundancy circuit.

A BiCMOS circuit includes a CMOS circuit for inverting data applied to an input terminal and a first bipolar transistor, having a base connected to an output point of this CMOS circuit, a collector connected to a power supply voltage and an emitter connected to an output terminal, for charging the output terminal. The BiCMOS circuit also includes a second bipolar transistor, having a collector connected to the output terminal, for discharging the output terminal, a first MOS transistor of a first conductivity type connected in parallel between the base and the collector of the second bipolar transistor and a second MOS transistor of the first conductivity type connected in series with the first MOS transistor and having a gate connected to an output point of the CMOS circuit. The Bi-CMOS circuit further includes a third MOS transistor of the first conductivity type connected between the input terminal and the gate of the first MOS transistor of the first conductivity type and having a gate receiving a first reference voltage, and a fourth MOS transistor of a second conductivity type connected between the first reference voltage and the gate of the first MOS transistor. A large variation width of an output voltage can be ensured, and hence the Bi-CMOS circuit normally operates even at a low voltage without any deterioration in terms of delay time.

Bi-CMOS circuit

There is provided a semiconductor device having a wiring configuration which can suppress an increase in the delay time of a wiring extending over the memory cell area even if the cell size is reduced. Wirings of preset wiring length are formed over a semiconductor substrate. A wiring of wiring length larger than that of the former wirings is formed over the former wirings with an inter-level insulation film disposed therebetween and the width of the latter wiring is made large. Thus, the wiring resistance is reduced and the wiring delay time can be effectively reduced. The semiconductor device is applied to a semiconductor memory or the like in which cell selection is made by use of the hierarchical structure such as a duplex word line system.

A semiconductor memory device including a plurality of cell array sections each having a plurality of memory cells disposed in a matrix form, the plurality of cell array sections being juxtaposed in a row direction. Main word lines, are each provided in common for all of the plurality of cell array sections in each row, a row select signal being applied to each main word line. Section word lines are connected to memory cells, in each cell array section at each row, for activating the memory cells. Section select lines are provided for each cell array section, a section selection signal being applied to each section select line. Logical circuits are provided for each cell array section, each logical circuit being connected to each main word line and the section select line, executing a logical operation between the row select signal and the section select signal, and activating the section select line when the logical operation result satisfies a predetermined logical condition. Each logical circuit includes a first inverter, a CMOS type second inverter and an N-channel transistor. Each main word line is connected to the input terminals of the first and second inverters. Each section select line is connected to the drain of the N-type transistor and the source of a P-channel transistor of the second inverter. The gate of the N-channel transistor is connected to the output terminal of the first inverter and each section word line is connected to the source of the N-channel transistor and the output terminal of the second inverter. Bit lines are connected to each memory cell for receiving data from a selected memory cell and outputting the data.

Semiconductor memory device for use an apparatus requiring high-speed

A semiconductor memory device includes an address input circuit for receiving an address signal and outputting an internal address signal corresponding to the received address signal; an address decoder for decoding the internal address signal and outputting a decoded signal; a memory cell array having a plurality of memory cells each capable of storing data, as selected by the decoded signal, the selected memory cell outputting memory cell data; and an output circuit for outputting a truth data and false data at the same time in accordance with the output memory cell data of the selected memory cell.

Growing community of inventors

Kawaguchi, Japan

Takayuki Harima