Spansion Llc.

Fujitsu Amd Semiconductor Limited

Monterey Research, LLC

Fasl LLC

Takayuki Enda

Hideo Takagi

Tsukasa Takamatsu

Miyuki Umetsu

Tatsuya Hashimoto

Toshiyuki Maenosono

Naoki Takeguchi

Masayuki Moriya

Taiji Togawa

Tatsuya Inoue

Taji Togawa

A semiconductor device includes a first metal layer provided above a semiconductor substrate, an interlayer insulating film provided above the first metal layer, a second metal layer that is provided in an opening formed in the interlayer insulating film and is in contact with an underlying layer, the second metal layer being connected to the first metal layer, and a first barrier layer that is provided between the second metal layer and the interlayer insulating film and has a different main composition from that of the underlying layer.

Method of forming a damascene interconnect on a barrier layer

Methods for detecting a void in an element portion of a semiconductor device having an element portion and a void detection structure are disclosed. As a part of the method, an insulating film is formed on a substrate, a plurality of holes is formed in the insulating film, and a metal portion is formed on the insulating film to fill the plurality of holes. The metal portion is polished until the insulating film is exposed and a recessed portion is formed in the void detection structure. It is determined if a void exists in the element portion of the semiconductor device by determining whether or not a void is exposed at a surface of the recessed portion of the void detection structure.

Semiconductor device with void detection monitor

The present invention provides a method of fabricating a semiconductor device including forming stop layers () that include silicon oxy-nitride films above a semiconductor substrate, forming a cover film () between and on the stop layers, in which a top surface of the cover film above a region between the stop layers is higher than top surfaces of the stop layers, and polishing the cover film to the stop layers by using ceria slurry, and also provides a semiconductor device including metal layers () provided above a semiconductor substrate, silicon oxy-nitride films () provided on the metal layers, and an embedded layer () provided between the metal layers to have a top surface substantially coplanar with top surfaces of the silicon oxy-nitride films. According to the present invention, it is possible to provide a semiconductor device having a film of excellent planarization on a surface thereof and fabrication method therefor.

Semiconductor device with stop layers and fabrication method using ceria slurry

Semiconductor device

Method for detecting a void

Devices and methods for plasma treated metal silicide layer formation are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a metal layer on a silicon substrate, exposing the metal layer to a plasma, and thermally treating the silicon substrate and the metal layer to form a metal silicide layer.

Plasma treated metal silicide layer formation

Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Method of fabricating semiconductor memory device and semiconductor memory device driver

A silicon nitride film for storing electric charge is formed on a semiconductor substrate while placing a tunnel oxide film in between, and the silicon nitride film is then subjected to hydrogen plasma treatment so as to effectively erase unnecessary charge stored therein during various process steps in fabrication of the semiconductor memory device, to thereby stabilize the threshold voltage (V) of the semiconductor memory device.

Growing community of inventors

Fukushima-ken, Japan

Takayuki Enda