Kabushiki Kaisha Toshiba

Takayoshi Shimazawa

Masataka Matsui

Fumihiko Sano

Goichi Ootomo

Katsuhiro Seta

A semiconductor circuit allows a timing adjustment after detailed routing without rearrangement and rerouting, an adjustment of delay variance due to process variation, and a delay adjustment even after chip formation using a primitive cell with a built-in means for adjusting delay time. The circuit connected between an input pad and an output pad, an operating method for the same, and a delay time control system circuit, which externally adjusts delay time of a plurality of control terminal-equipped/variable capacitance embedded buffers configures a semiconductor circuit. The structure includes: a first buffer connected between the input pad and the output pad; and a plurality of capacitances connectable in parallel between a fixed potential and a current flowing path, which is positioned between the first buffer and the output pad, and that controls connection between each of the plurality of capacitances and the output pad.

Semiconductor circuit, operating method for the same, and delay time control system circuit

The proposed variable length coder can detect the start codes appropriately, while reducing the circuit scale thereof. The variable length code decoding apparatus, comprises: an interface section (2) having a plurality of registers (R20, R21, R22) each having a predetermined number of bits, for storing variable length code data in each of the registers in first-in first-out status; a shift circuit (3) for receiving data transferred from a predetermined number of the adjacent registers of the interface section and for shifting the received data by a number of bits corresponding to an applied shift signal, to select a start code head; and a start code detecting circuit (6) for executing detection operation by receiving data supplied from a predetermined number of the adjacent registers of the interface section, by detecting presence or absence of a start code on the basis the received data kept in byte-aligned status to output a start code presence and absence signal, and by outputting a start code shift length signal indicative of a byte from which a head bit of the start code begins in unit of byte, the start code shift length signal being applied to the shift circuit as the shift signal.

Variable length code decoding apparatus having parallel start code and

A first and second barrel shifters (BSA0 and BSA1) are connected directly without intervening any pipe-line register between the two, and a sense amplifier (R3A0) is provided at an output side of the second barrel register (BSA1). Further, the circuit patterns of the first and second barrel shifters are formed being overlapped with each other in such a way that the elements of one of the first and second barrel shifters are formed at the dead space of the other of the two barrel shifters to reduce the pattern area. In the shift circuit and the variable-length decoder, the data lines of the barrel shifters can be minimized in size and width.

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Yokohama, Japan

Takayoshi Shimazawa