Sanyo Electric Co., Ltd.

Takayoshi Higashino

Tetsuro Asano

Koichi Hirata

Yasoo Harada

Mikito Sakakibara

Shigeharu Matsushita

Toshikazu Hirai

Takashi Yamada

Masao Nishida

Emi Fujii

Satoshi Terada

Akihito Nagamatsu

Daijirou Inoue

Takashi Kurose

Kouji Matsumura

Shigeyuki Murai

A compound semiconductor switching device is based on a designing guideline that isolation should be assured by reducing the gate width of switching FET, thereby reducing the capacitance of the FET. Proper isolation between the two signal passes IS obtained with a FET gate width of about 700 &#x3bc;m or smaller at a signal frequency of about 2.4 GHz or higher, without employing a shunt FET.

Compound semiconductor switching device for high frequency switching

The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &#x3bc;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &#x3bc;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &#x3bc;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

Compound semiconductor device

The conventional compound semiconductor switching device is prone to have a large chip size as the gate width needs to be large for achieving a low insertion loss and the separation between the connecting pad and the circuit wiring needs to be larger than 20 &mgr;m for obtaining a proper isolation between them. The overall chip size is reduced, first, by reducing the gate width of the switching FET operating at frequencies above 2.4 GHz to 700 &mgr;m or smaller together with the omission of the shunt FET, and, then, by reducing the separation between the connecting pad and the circuit wiring to 20 &mgr;m or smaller. This reduction of the separation is made possible by the introduction of an insulating film and a impurity region between the outermost portion of the connecting pad and the substrate for preventing the extension of the depletion layer. The manufacturing method of this device does not need any additional processing step for accommodating the above structure, and is capable of producing a device having a size of one fifth of the conventional device.

Compound semiconductor device with depletion layer stop region

A negative voltage generating circuit includes an oscillating unit constructed of a ring oscillator for outputting a pulse signal with a high frequency and a polarity inverting unit in which the pulse signal is inputted to charge negative voltage. This negative voltage generating circuit is miniaturized and outputs a stable negative voltage. Further, the negative voltage to be outputted can be controlled by varying a resistance value through a control of an FET in a voltage controlling unit.

Negative voltage genarating circuit

A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.

Method of doping, semiconductor device, and method of fabricating

A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.

Method of doping a group III-V compound semiconductor

A field-effect transistor including a first channel layer, formed in contacting relationship with a gate electrode, and a second channel layer, formed on one side or both sides of the first channel layer in non-contacting relationship with the gate electrode, the carrier concentration in the second channel layer being higher than that in the first channel layer but lower than that in high-impurity concentration active layers forming drain and source regions. The field-effect transistor employs an offset gate configuration in which the gate electrode is formed in contacting relationship with the first channel layer at a position nearer to the high-impurity concentration active layer forming the source region than to the high-impurity concentration active layer forming the drain region. A dummy gate is formed and ion implantation is performed from two different angles using the dummy gate as a mask, thereby efficiently forming the source region, drain region, and second channel layer in a sequence of successive processing steps. By combining the suitably patterned first and second ion shielding layers, the gate to source electrode spacing and the gate to drain electrode spacing are controlled by the accuracy to which the second ion shielding layer can be formed.

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Neyagawa, Japan

Takayoshi Higashino