Kabushiki Kaisha Toshiba

The University of Tokyo

Semiconductor Technology Academic Research Center

Renesas Electronics Corporation

Tokyo Shibaura Denki Kabushiki Kaisha

Japan Science and Technology Agency

Osaka University

Keio University

The Foundation for the Promotion of Industrial Science

Microcomputer Engineering Ltd.

Shaibaura Denki Kabushiki Kaisha

Takayasu Sakurai

Makoto Takamiya

Kazutaka Nogami

Tetsuya Iizuka

Kazuhiro Sawada

Tadahiro Kuroda

Mitsuo Isobe

Ken Takeuchi

Hiroyuki Hara

Koichi Ishida

Tadashi Yasufuku

Hiroshi Kawaguchi

Tsuyoshi Sekitani

Fumitoshi Hatori

Takayuki Ohtani

Toshiro Hiramoto

Teruyoshi Hatanaka

Tokihiko Mori

Hiroshi Fuketa

Makoto Suzuki

Takao Someya

Syuso Fujii

Tetsuya Fujita

Naohiro Matsukawa

Takafumi Uemura

Tetsu Nagamatsu

Shusuke Yoshimoto

Tsukasa Shirotori

Yoshinori Watanabe

Katsuhiro Seta

Teppei Araki

Yuki Noda

Makoto Ichida

Hisashi Ueno

Masanori Uchida

Daisuke Mizoguchi

Gensoh Matsubara

Akira Aono

Noriyuki Miura

Shunta Iguchi

Lee-Sup Kim

Sungjun Lee

Takashi Inukai

Po-Hung Chen

Yusmeeraz Binti Yusof

Robert Saliba Fayez

Kohei Onizuka

A wiring sheet includes one or more carbon wires each of which is one of a signal line and a power supply line, and which are conductors including carbon as a main material and have flexibility; and an insulation sheet that encloses substantially an entirety of the one or more carbon wires, includes an electrical insulator as a main material, and has flexibility.

Wiring sheet, sheet-shaped system, and structure operation support system

An object to provide an electric device easy to manufacture, extensible and of high quality. The electric device comprises a plurality of module boards, the module boardspiled up on one another, each of the module boardsprovided with an electrodeon its surface, the electrodeson the piled-up module boardsgenerally positioned along a vertical straight line; and a connectorconnecting the module boards, the connectorincluding a body portion, the body portionelectrically connecting the electrodespositioned along the vertical straight line, and a holderholding the body portion, the holderincluding a board engagement portion and a holder connecting portion, the board engagement portion engaging with the module boardso that the connectoris mounted on the module board, and the holder connecting portion engaging with another holder connecting portion so that the connectoris coupled to another vertically adjacent connector

Electric device

A signal detection device includes: multiple electrodes that are arranged to come into contact with a subject that generates a signal; an electrode signal selection unit that alternatively selects one signal from signals on the multiple electrodes based on a selection signal; an amplification unit that amplifies the signal that is selected by the electrode signal selection unit; and a flexible substrate on which the multiple electrodes, the selection unit, and the amplification unit are formed, in which the amplification unit is formed on the substrate to form a laminated structure together with the multiple electrodes and the selection unit.

Signal detection device, signal detection method, and method of manufacturing signal detection device

For example, an averaging circuit includes first to third capacitors and a controller. The controller causes a first first-stage average voltage to be applied to a first capacitor, the first first-stage average voltage being an average of a first voltage applied to the first capacitor and a second voltage applied to a second capacitor, causes a second first-stage average voltage to be applied to the second capacitor, the second first-stage average voltage being an average of a third voltage applied to the second capacitor and a fourth voltage applied to a third capacitor, and causes a first second-stage average voltage to be applied to the first capacitor, the first second-stage average voltage being an average of the first and second first-stage average voltages applied to the first and second capacitors.

[object Object]

According to one embodiment, an oscillator circuit includes a resonant circuit and first and second negative-resistance circuits. Each of the first and second negative-resistance circuits includes a first power-supply terminal, a second power-supply terminal, an input terminal and an output terminal. The first and second negative-resistance circuits are connected in series between a first power supply and a second power supply at the first and second power-supply terminals, and connected parallel to the resonance circuit at the input and output terminals.

Oscillator circuit

A clock generation circuitincludes a resonant reactor connected with a half voltage supply point TV, a resonant capacitor CL connected between a ground voltage supply point TVss and an output terminal TVout, a transistor MPconnected between the resonant reactor Lr and the resonant capacitor CL, and a transistor MNconnected with the output terminal TVout. In this configuration, signals in a wide range of frequencies can be output with low power consumption by adjusting the time when a clock signal &#x3c6;1 applied to the gates of the transistors MPand MNis high.

Signal transmission circuit

A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Integrated circuit device

In a voltage detecting circuit, a transistor is configured as a P-type MOSFET, and includes a source connected with an input terminal, a gate connected with a ground voltage terminal and a drain connected with an output terminal. A transistor is configured as a P-type MOSFET, and includes a gate and a source connected with the output terminal and a drain connected with the ground terminal. Gate width and gate length of the transistor and gate width and gate length of the transistor are adjusted so that source-drain current flowing between the source and the drain of the transistor becomes equal to source-drain current flowing between the source and the drain of the transistor when the voltage applied to the input terminal is set to be preset trigger voltage. This configuration accomplishes detecting that the input voltage exceeds the trigger voltage with simple configuration.

Voltage detecting circuit

The interposeris disposed on an upper surface of the stacked structureformed by stacking a plurality of a DRAM chipand a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished.

Stacked structure with a voltage boosting supply circuit

The voltage Vdd is set to be lower than in the normal operation (step S), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps Sand S). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit

The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.

Integrated circuit device having a plurality of integrated circuit chips and an interposer

An electronic circuit capable of efficiently transmitting signals in a case where signals are transmitted over substrates with three or more substrates three-dimensionally mounted. In the present invention, LSI chips are stacked in three layers, and a bus is formed over three chips. The first through the third transmitter coils 13, 13, 13and the first through the third receiver coils 15, 15, 15are formed by wiring on the first through the third LSI chips 11, 11, 11. These three pairs of transmitter and receiver coils are disposed so that the centers of the openings thereof are coincident with each other, whereby three pairs of transmitter and receiver coils 13 and 15 form inductive coupling to enable communications. The first through the third transmitter circuits 12, 12, 12are connected to the first through the third transmitter coils 13, 13and 13, respectively, and the first through the third receiver circuits 14, 14, 14are connected to the first through the third receiver coils 15, 15, 15, respectively.

Electronic circuit

A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.

Self-aligned row-by-row dynamic VDD SRAM

A voltage control circuit is connected to a voltage source. The voltage control circuit changes voltages of n different values and outputs them to an output node of the voltage control circuit according to control signals. A first switch element is connected between the output node of the voltage control circuit and a reference voltage node, and a second switch element is connected between the output node of the voltage control circuit and an output node of the voltage source. The first switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a first voltage to a second voltage that is lower than the first voltage, and the second switch element is controlled so as to be conductive when the voltage control circuit changes the voltage of the output node from a second voltage to a first voltage.

Power supply circuit capable of rapidly changing output voltages

A semiconductor integrated circuit of the present invention has a CMOS circuit composed of a first MOSFET and a switch composed of a second MOSFET which are connected in series. Then, a circuit-driving voltage and a switch-driving voltage are applied independently to the CMOS circuit and the switch The switch-driving voltage is larger than the circuit-driving voltage.

Semiconductor integrated circuit

Growing community of inventors

Tokyo, Japan

Takayasu Sakurai