Fujitsu Corporation

Takayasu Mochida

Takaaki Kato

Yoshio Morita

Mitsurou Nakajima

A parallel processing device includes a processing sequence management unit that reads commands of the command corresponding to a parallel processing start bit to the command corresponding to a parallel processing completion bit from a sequence command storage in sequence to make the sequence command storage output the commands to a first address management unit and a second address management unit, the first address management unit refers to the sequence commands read from the sequence command storage in order from the head to find the command that a first processing execution unit executes, and then instructs the first processing execution unit to execute the command, and the second address management unit refers to the sequence commands read from the sequence command storage in order from the head to find the command that a second processing execution unit executes, and then instructs the second processing execution unit to execute the command.

Parallel processing device

A logic device re-programmable without terminating operation. In the logic device, a logic circuit is configured and maintained based on logic circuit configuration data for implementing a desired function. The logic device comprises: a memory holding the logic circuit configuration data for configuring and maintaining the logic circuit; and an address controller for writing, in an unused area of the memory, logic circuit configuration data for configuring and maintaining one or more additional logic circuits without terminating operation of the logic device. It is an object of the present invention to provide a logic device in which data re-writing, such as addition of functions and correction of problems, is available as required, without terminating operation of the device.

Logic device re-programmable without terminating operation

A shaper circuit is provided in a line adapter, not in an ATM switch. A billing section is provided on the output side of the shaper circuit. The shaper circuit is configured to output M cells for N cell slots at a temporally smooth rate, where M and N are integers. This configuration serves to optimize buffer capacity for shaping, prevents charging for discarded cells, and allows a full rate setting matched to a line speed.

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Yokohama, Japan

Takayasu Mochida