Panasonic Intellectual Property Management Co., Ltd.

Panasonic Semiconductor Solutions Co., Ltd.

Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Nuvoton Technology Corporation Japan

Takayasu Kito

Shinichi Ogita

Hiroyuki Amikawa

Makoto Ikuma

Tetsuya Abe

Yoshiaki Satou

Masaaki Yanagida

Junichi Matsuo

Hiroshi Fujinaka

Yasuyuki Endoh

Takahiro Muroshima

Katsumi Tokuyama

Yutaka Abe

Norihiko Sumitani

Mitsuhiko Otani

Akira Kawabe

Kenichi Origasa

Masahiro Higuchi

Naohisa Hatani

Kouji Yamaguchi

A solid-state imaging device includes: a plurality of pixel circuits arranged in rows and columns; a plurality of selector circuits that each receive, as inputs, two pixel signals corresponding to two columns different from each other; k column AD conversion circuits that perform AD conversion on pixel signals output from the plurality of selector circuits, k being an integer greater than or equal to two; and m column AD conversion circuits that are provided redundantly. In the solid-state imaging device, the plurality of selector circuits selectively exclude, from among the k column AD conversion circuits and the m column AD conversion circuits, m column AD conversion circuits corresponding to m columns adjacent to each other, and associate k pixel signals output from the plurality of pixel circuits with k column AD conversion circuits which have not been excluded.

Solid-state imaging device with redundant ad conversion circuits and selective exclusion

A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Solid-state imaging apparatus and imaging apparatus

A solid-state imaging device includes: a pixel including a photoelectric converter that generates a charge and a charge accumulator that converts the charge into a voltage; a controller that causes the pixel to perform exposure in a first exposure mode and convert the charge into the voltage with a first gain to output a first pixel signal, and causes the pixel to perform exposure in a second exposure mode and convert the charge into the voltage with a second gain to output a second pixel signal, the second exposure mode being shorter in exposure time than the first exposure mode, and the second gain being lower than the first gain; and a signal processor that synthesizes the second pixel signal after amplification and the first pixel signal.

Solid-state imaging device and imaging apparatus

A solid-state imaging device includes: a pixel array unit in which a plurality of pixels are arranged in rows and columns; a plurality of column signal lines which are provided in one-to-one correspondence with pixel columns; a column processor including a plurality of column AD circuits provided in one-to-one correspondence with the plurality of column signal lines; a power supply variation detector which is connected to a power supply wire through which a power supply voltage is transmitted to each of the pixels, and which detects, in correspondence with pixel rows, power supply variation components attributed to variations in the power supply voltage; and a power supply variation corrector which corrects, for each of the pixel rows, a pixel signal detected by the column processor, using the power supply variation components detected by the power supply variation detector.

Solid-state imaging device and imaging device capable of correcting pixel signal

A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

An imaging device having a pixel including a photoelectric converter that converts incident light into charges, and a reset transistor having a first source, a first drain and a first gate, one of the first source and the first drain coupled to the photoelectric converter. The imaging device further including first voltage generating circuity that generates a first voltage; second voltage generating circuity that generates a second voltage, the second voltage generating circuity being different from the first voltage generating circuity; and first switching circuity that causes either the first voltage generating circuity or the second voltage generating circuity to selectively couple to the other of the first source and the first drain of the reset transistor.

Imaging device including pixel

An imaging device comprising: a pixel comprising a photoelectric converter and a reset transistor having a source and a drain one of which is electrically connected to the photoelectric converter; a first voltage generating circuit for generating a first voltage; a second voltage generating circuit for generating a second voltage identical or equivalent to the first voltage; and a first switching circuit having a first input terminal electrically connected to the first voltage generating circuit, a second input terminal electrically connected to the second voltage generating circuit, a first output terminal electrically connected to the other of the source and the drain of the reset transistor. The first switching circuit electrically connects one of the first and second input terminals to the first output terminal selectively in a period when the photoelectric converter is reset. The photoelectric converter is reset by use of the first voltage or the second voltage.

A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion () based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (). A test can be performed by supplying a test signal in place of the input analog signal. A control portion () performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal. A test signal can be input with a small-scale configuration, without providing a test signal line separately from a line used for normal operation.

Pipeline A/D converter

In each of a plurality of stages, an input analog signal is quantized, so that a digital signal corresponding to each part of bits is generated. ADA conversion portion generates an analog reference signal based on the digital signal, and a remainder operation portion performs addition/subtraction and amplification by a predetermined factor with respect to the input analog signal. Then, the signal thus obtained is supplied to a subsequent stage. The DA conversion portion in the first stage where A/D conversion of a plurality of bits is performed includes primary voltage supply portions capable of outputting a reference voltage at one of a plurality of levels, and an auxiliary voltage supply portion capable of outputting a reference voltage at an auxiliary level different from the above-described level. The respective voltage supply portions selectively output the reference voltages based on a digital signal generated by an AD conversion portion. Based on a combination of the output reference voltages, the analog reference signal in accordance with the digital signal is generated. It is possible to reduce power consumption while suppressing an increase in the area of an element.

Pipeline A/D converter and digital camera

A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements Cand Cin a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k&#x2212;1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.

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Osaka, Japan

Takayasu Kito