Renesas Electronics Corporation

Fujitsu Corporation

Kokusai Denshin Denwa Kabushiki Kaisha

Renesas Technology Corp.

Hitachi Chemical Company, Ltd.

Imec

Imec Vzw

Takaya Yamamoto

Hideo Nakane

Keisuke Kimura

Yuichi Okuda

Tatsuji Matsuura

Takashi Oshima

Kazuo Sakai

Shigeyuki Akiba

Keiichi Otani

Shu Yamamoto

Kazuo Sasaki

Yuichi Matsushima

Atsuo Serikawa

Mari Iwasaki

Yotaro Yatsuzuka

Daisuke Abe

Katsuyuki Yamazaki

Yoshitaka Takezawa

Takayuki Ogawa

Masumi Kasahara

Jan Craninckx

Yukio Noda

Katsuyuki Yamamoto

Yukio Nakagome

Kenichi Iga

Chuichi Ota

Akiko Yoshida

Masaharu Matsumoto

Kitsutaro Amano

Yasuharu Suematsu

Naoshi Kayashima

Koji Yano

Kenji Orita

Motoharu Usumi

Ryuichi Ujiie

Yoshio Itaya

Yoshitaka Jingu

Masanobu Kodaira

Shigehisa Arai

Shihui Song

Junya Kudo

Tomoko Kishi

Eiji Okano

An information processing apparatus includes a processor that detects positions of ball candidates from a plurality of time-series image frames. The processor adds a position of a second ball candidate to a second image frame subsequent to a first image frame based on a position of a first ball candidate and movement definition information. The first ball candidate is detected from the first image frame. The movement definition information defines a characteristic of a movement of a ball. The processor generates a plurality of trajectory candidates by combining a plurality of ball candidates detected from image frames of different times. The processor evaluates the plurality of trajectory candidates to determine a ball trajectory. The processor interpolates, when the ball trajectory is interrupted, between a starting point and an ending point of the interruption with a trajectory of a first person who moves from the starting point to the ending point.

Image processing method and information processing apparatus

A camera, a storage device, and an image processing apparatus are included. The storage device stores a plurality of captured images that are captured by the camera. The image processing apparatus estimates a region of an object included in a captured image of a current time based on a captured image of a previous time, for each of multiple objects included in the captured image of the current time. The image processing apparatus evaluates whether to correct the estimated region of each object based on a combination region in which the estimated regions of the respective objects are combined, and on a difference region that is identified by a background image and the captured image of the current time. The image processing apparatus corrects the estimated regions of the respective objects based on a result of evaluation.

Image processing system, image processing apparatus, and image processing method for object tracking

A prepreg mica tape includes: a backing material (); a boron nitride-containing layer () that is provided on or above one surface of the backing material () and that includes a boron nitride particle () and a first resin (); and a mica-containing layer () that is provided on or above the surface of the backing material () on which the boron nitride-containing layer () is provided and that includes mica () and a second resin ().

Prepreg mica tape and coil using same

The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor deviceincludes: an AD converter; a digital assist circuitthat corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter; and a failure detection circuitthat detects whether the AD converterhas a failure based on a correction amount by the digital assist circuit. The semiconductor deviceis therefore able to detect the excessive variation among the elements that constitute the AD converteras a failure.

Semiconductor device and failure detection method

An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

A/D converter circuit and semiconductor integrated circuit

A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.

Semiconductor device

There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.

Passive amplification circuit and analog-digital convertor

To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.

Electronic system and operating method thereof

A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Semiconductor integrated circuit device

Growing community of inventors

Kanagawa, Japan

Takaya Yamamoto