Toshiba Memory Corporation

Kioxia Corporation

Takaya Handa

Junichi Sato

Akio Sugahara

Noriyasu Kumazaki

Masashi Yamaoka

Yuzuru Shibazaki

Norichika Asaoka

Kazuto Uehara

Bushnaq Sanad

Yuri Terada

Ryosuke Isomura

Yoshihisa Kojima

Kiyotaka Iwasaki

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Memory device which generates operation voltages in parallel with reception of an address

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

Memory system

According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

Growing community of inventors

Yokohama Kanagawa, Japan

Takaya Handa