Fujitsu Corporation

Takaya Chiba

Hirotaka Tamura

Satoshi Ide

Kohtaroh Gotoh

Hiroyuki Nobuhara

Hideki Ishida

Takuya Saze

A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy

A clock recovery circuit has a boundary detection/discrimination circuit to detect and discriminate a boundary in an input signal in accordance with a first signal. The clock recovery circuit performs clock recovery by controlling the timing of the first signal in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit is varied by controlling the first signal.

Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction

A timing signal generating circuit receives a plurality of input signals of differing phases and generates a timing signal having a phase intermediate therebetween. The timing signal generating circuit has a plurality of current polarity switching circuits, and a voltage level correction circuit. Each of the current polarity switching circuits is provided between a plurality of current sources and acts to switch an output current polarity in accordance with a corresponding one of the input signals. The voltage level correction circuit corrects the voltage level of a phase-combined signal produced by combining weighted outputs of the plurality of current polarity switching circuits.

Timing signal generating circuit and receiver circuit designed to speed up signal transmission

The present invention discloses a signal amplifier circuit used in, for example, a receive portion in an optical communication system, and including an automatic threshold value setting portion to automatically set a threshold value depending upon a '1' side level and a '0' side level of an input signal, an automatic gain control amplifying portion to take as inputs the input signal and the threshold value from the automatic threshold value setting portion so as to perform differential amplification, and a gain control portion to detect amplitude information of the input signal so as to feed a gain control signal according to amplitude of the input signal to the automatic gain control amplifying portion as a feedforward signal. It is thereby possible to avoid limitation of a signal amplified in the signal amplifier circuit at a time of reproduction of a pulse signal, and compensate for offsets present in circuits so as to suppress a variation in pulse width of the output signal.

Signal amplifier circuit

An automatic threshold control circuit includes a bottom detection circuit, a relative peak detection circuit, and a voltage divider circuit. The bottom detection circuit detects an absolute minimum level of an input signal, and the relative peak detection circuit detects, in accordance with the input signal, a maximum level relative to the minimum level detected by the absolute bottom detection circuit. Further, the voltage divider circuit generates a threshold level by dividing the absolute minimum level and the relative maximum level in a predetermined ratio. Using this configuration, a signal amplifying circuit can be constructed that is capable of accurately reproducing digital signals at all times regardless of variations in the amplitude or the DC level of the input signal.

Growing community of inventors

Sapporo, Japan

Takaya Chiba