Fujitsu Corporation

Takatoshi Muraoka

Shigeru Nagasawa

Minoru Koshino

Keiichiro Uchida

Masanori Motegi

A memory access control system in a vector processing system comprises a memory unit, a memory device, address holding registers, a shift register and data buffer registers. The memory access control system distinguishes each vector data read out from the memory unit based upon the address holding registers by the output of the shift register. The shift register stores vector element numbers indicated by the memory device and transfers same to the data buffer registers. Each number from 0 to n-1, of a vector A composed of n elements a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-1, is a vector element number and each data, from a.sub.0 to a.sub.n-1, is vector element data.

Memory access control system in vector processing system

A system for controlling the addition of signed binary numbers represented with N bits, of the 2's complement notation, is disclosed which includes addend and augend sign control circuits, and an adder circuit comprising a carry save adder and a carry proper gate adder. The addend sign control circuit receives an operation command sign signal (B, --B, .vertline.B.vertline. or --.vertline.B.vertline.) for the addend, which designates the addend of the certain type (B, .vertline.B.vertline. or --.vertline.--B.vertline.) to be applied directly to the carry save adder and designates the addend of another type (--B, .vertline.--B.vertline. or --.vertline.B.vertline.) to be applied to the carry save adder through a 1's complementer. The augend sign control circuit functions similarly for the augend being applied to the carry save adder. A corrective number (0, 1 or 2) is applied to the adder circuit which corresponds to neither, one, or both the addend and augend being applied to the adder circuit through their respective 1's complementer.

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Kyoto, Japan

Takatoshi Muraoka