S3 Incorporated, Inc.

S3 Graphics Co., Ltd.

Spatial Photonics, Inc.

Neomagic Corporation

Faust Communications, LLC

Linkup Systems Corporation

Takatoshi Ishii

Edmund Cheung

Nikhil Balram

Qiang Li

Lutz Filor

Sai-Kit Tong

Julie Zhang

Thomas C Young

Yves C Faroudja

Sherwood Brannon

David L Medin

Yonggab Park

Neal D Margulis

A colored light generating element can be configured to, while in an active state, pulse between an off state and an on state. A substantially constant offset voltage or current can be applied to the colored light generating element during a predetermined time interval when the light generating element is in the off state so as to cause the colored light generating element to emit, during the off state, some amount of light greater than a minimum amount of light that the light generating element is capable of generating while part of an active system. In some implementations, two or more offset voltages or currents can be applied. Implementations may include a preprocessor configured to receive an image signal and optimize color saturation of the image signal, such as by limiting and non-linearly increasing color saturation. Implementations may include multiple colored light generating elements.

Color display

Methods, systems, and apparatus, including computer program products, for reducing artifacts in a color sequential display system. A frame of a digital image is displayed by receiving frame data, determining dither patterns, applying the dither patterns to the data, and displaying the dithered data. Each pixel of a frame of a digital image is displayed by receiving pixel data, grouping the pixel data for the color channels of the image into a plurality of sub-groups of pixel data; and displaying the pixel according to a sequence that separates each pair of sub-groups for a color channel by a sub-group for another color channel. Modified pixel data can be generated by replacing parent bits in the pixel data with corresponding pluralities of divided child bits, where all the child bits for a given parent bit have a divided weight that adds up to the parent bit's weight.

Reducing image artifacts in a color sequential display system

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator

A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,.eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

A display subsystem supports both normal mode and portrait mode displays. In normal mode, the scan starts at the upper left comer of the display. In portrait mode, the scan starts at the lower left comer of the display. The display subsystem includes a dual mapped display memory having a normal mode display area and a portrait mode display area. The portrait mode display area is defined by X-ofst and Y-ofst. X-ofst is a power of two that is greater than the real X-ofst supported by the display in portrait mode. Address requests from the CPU or software use high order bits to specify whether the address is in the normal or portrait mode display area. In addition, address requests to the portrait mode display area use the address space defined by X-ofst and Y-ofst. When the address request specifies the portrait mode display area, the address of the request is translated to account for the different mode of the display. Since X-ofst is a power of two, the X-coordinate of the display location specified by the address can be determined without a division operation, thereby allowing for fast address translation. Logic within the display subsystem rapidly translates the address and supports a range of Y-ofst values.

Hardware portrait mode support

A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.

Flat-panel display controller with improved dithering and frame rate control

A video deinterlacing system receives interlaced video data at a non-deterministic rate and generates non-interlaced data as a function of the interlaced video data. The system includes processing units, some of which require clocking rates that differ from clocking rates required by other processing units. A timing generator responds to a base clock and to a data valid signal, that indicates arrival of a portion of the interlaced video data, to cause generation of a plurality of enable signals. Each of the enable signals operate to enable a corresponding one of the clocking rates required by the processing units. Video capture can be performed by causing capture of video frames that meet or exceed a specified quality level. The quality of the captured, still image, video can be improved by disabling certain enhancement functions performed to improve moving video images.

System and method for selective capture of video frames

Frame-rate control electronic provides gray-scale display control algorithm for STN LCD devices and constant brightness display with randomized pattern algorithm. Even distribution control of phase number reduces screen flicker and stabilizes gray-scale display. Randomized and scrambled phase number control eliminates screen beating artifacts, such as when image includes dither and checker patterns. Programmable parameters, such as tuning value, phase number matrices, and frame offset numbers, may be chosen flexibly to optimize conditions to certain display.

Apparatus and method for gray-scale and brightness display control

A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ring buffers (MPRBs) in an internal memory and/or an external display memory. Each MPRB comprises a plurality of addressable storage location holding video data and linked in a logical ring configuration. In addition, each MPRB has at least three ports, selected from write ports for writing to the addresses of the storage locations and read ports for reading from the addresses. Each read port in the MPRB is disposed a certain distance, or number of storage locations, behind a write port. This distance defines the size of the memory emulated by the MPRB. By positioning multiple read ports at different distances from the write ports, a single MPRB can emulate several different memories of different sizes. Since a write port needs to write the video data to the MPRB only once and the data need not be moved within the MPRB, the memory bandwidth consumed by the MPRB is substantially less than that required by the discrete memories.

Multiple-port ring buffer

Timing and control for deinterlacing and enhancement of

A flat-panel display controller generates signals to cause display of images on TFT and STN type flat-panel displays. The display controller includes dither logic and frame rate control logic. The dither logic performs dynamic and distributed dithering on pixel data to generate smooth 16 gray-shade images on the display. The dynamic and distributed dithering capabilities are programmable. Dynamic dithering is programmable to specify, two-phase, four-phase or eight-phase mixes.to generate signals for use by TFT and STN type flat-panel displays. The frame rate control logic is responsive to the dither logic and performs frame rate control on the dithered signals using stored values indicative of average pixel luminescence to generate 256 gray-shades.

Flat-panel display controller with improved dithering and frame rate

A dynamic random access memory (DRAM) circuit operates in burst mode when a row address strobe (RAS) signal is applied while an output enable/burst enable signal is also applied thereto. During burst mode, a column address strobe (CAS) signal is toggled to access digital data from sequential column addresses within a given row.

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Sunnyvale, CA, United States of America

Takatoshi Ishii