Nippon Telegraph and Telephone Corporation

Takatomo Enoki

Hideyuki Nosaka

Koichi Murata

Munehiko Nagatani

Shogo Yamanaka

Kimikazu Sano

Kiyomitsu Onodera

Tetsuya Suemitsu

Kunihiro Arai

Naoteru Shigekawa

A vector sum phase shifter includes a 90&#xb0; phase shifter () which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner () which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (). The control circuit () includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.

Vector sum phase shifter, optical transceiver, and control circuit

A voltage generator () includes a resistor ladder including resistors (-) which divide a supplied voltage to generate a plurality of reference voltages, a resistor () provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor () provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.

Voltage generator, control circuit, vector sum phase shifter, and optical transceiver

A Schottky barrier layer in separate regions between a source electrode and a gate electrode and between a drain electrode and the gate electrode is completely covered with an etching stopper layer. The gate electrode is separated from a cap layer.

Heterojunction field effect transistor and method of fabricating the same

A heterojunction field-effect transistor includes a first electron transit channel formation semiconductor layer formed on a substrate and consisting of a compound semiconductor, a first electron supply semiconductor layer formed on the first electron transit channel formation semiconductor layer and consisting of a compound semiconductor, a gate electrode, a source electrode, and a drain electrode formed on the first electron supply semiconductor layer, and a second electron transit channel formation semiconductor layer formed between the substrate and the first electron transit channel formation semiconductor layer. The second electron transit channel formation semiconductor layer consists of a cmpound semiconductor which has electron affinity smaller than that of the first electron transit channel formation semiconductor layer and larger than that of the first electron supply semiconductor layer, and is different from the first electron transit channel formation semiconductor layer in field strength position where a maximum value of an electron velocity is obtained, and is arranged such that an energy level on a bottom of an electron conduction band of the second electron transit channel formation seimconductor layer is substantially the same as a Fermi level.

Growing community of inventors

Kanagawa, Japan

Takatomo Enoki