Fujitsu Corporation

Fijitsu Limited

Takato Noda

Takumi Takeno

Yoshio Hirose

Takumi Kishino

Yasutomo Sakurai

Koichi Odahara

Toru Watabe

Shinya Katoh

Kazuhiro Nonomura

Takaharu Ishizuka

Takayuki Shimamura

Shinya Kato

Fumitake Sugano

Katsunori Takeshita

Takumi Nonaka

Yasuhide Shibata

To provide a cache-tag control method capable of correcting an error and capable of keeping a high-speed operation of a system at the same time. A true-tag with a parity code attached and a shadow-tag having an inverted polarity of the true-tag are stored respectively in separate addresses within a cache tag-RAM. At the time of retrieving the tags, both the true-tag and the shadow-tag are checked respectively to see whether there is an error in each tag. When an error has been detected, a hit decision is made by using a tag in which there is no error. Further, data within the cache tag-RAM is updated by using the tag in which there is no error, thereby correcting the error.

Cache-tag control method in information processing apparatus having cache, with error checking mechanism in cache tag, and information processing apparatus using this control method

Processing units each having a first memory and a system controller are interconnected over a bus. The system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead, and thus controls access to memories or memory access requested by the processing units. In the information processing system, a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis. Since access to the memories and tags on the interleaving basis is thus enabled, even if the number of processing units increases, competition for the memory access control units subsides and the efficiency of memory access improves.

Information processing system in which memory devices and copies of tags are accessed in response to access requests issued from plurality of processing units

A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.

Information processing system

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Kawasaki, Japan

Takato Noda