Matsushita Electric Industrial Co., Ltd.

Takato Handa

Hiroyuki Umimoto

Tetsuya Ueda

Kazumi Kurimoto

Tadashi Kadowaki

A first doped layer of a conductivity type opposite to that of source/drain regions is formed in a semiconductor substrate under a gate electrode. A second doped layer of the conductivity type opposite to that of the source/drain regions is formed in the semiconductor substrate below the first doped layer. The first doped layer has a first peak in dopant concentration distribution in the depth direction. The first peak is located at a position shallower than the junction depth of the source/drain regions. The second doped layer has a second peak in dopant concentration distribution in the depth direction. The second peak is located at a position deeper than the first peak and shallower than the junction depth of the source/drain regions. The dopant concentration at the first peak is higher than that at the second peak.

Semiconductor device and method for fabricating the same

An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.

Semiconductor device including a MISFET and a MIS capacitor

A hard mask which has an opening for exposing a p-type region defined in a silicon substrate and is made of, for example, a BPSG film is formed. Then, the hard mask is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask as a mask, thereby forming an n layer having an LDD structure. Thereafter, the implantation hard mask is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

Growing community of inventors

Shiga, Japan

Takato Handa