Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Software Engineering Company, Ltd.

Takashige Kubo

Hidenori Umeno

Nobutaka Hagiwara

Hideo Sawamoto

Hiroaki Sato

Toshiaki Arai

Toshiyuki Kinoshita

Yasufumi Yoshizawa

Yoshio Ukai

Takao Sato

Kenichi Wada

Taro Inoue

Taketoshi Sakuraba

Shunji Tanaka

Masaichiro Yoshioka

Nobutaka Amano

Kaoru Moriwaki

Minoru Shibamiya

Takao Shinsha

Hiroshi Ikegaya

Nobuyoshi Sugama

Kimio Ooe

Junji Koshishita

Shigeo Takasaki

Masato Morita

Yoshinori Sakataya

Mitsuhiro Hikosaka

Yoji Tsuchiya

Jinichi Imura

Yasuo Kubo

Hiromichi Mori

Syunpei Kawasaki

Kazumasa Shima

Keiho Akiyama

In a computer system having a central processing unit, a main storage and at least one I/O device, a plurality of operating systems (OS) can simultaneously run under the control of a control program. For executing an I/O instruction using a central processing unit, a plurality of resident areas of said main storage which do not overlap one another are assigned, under the control of the control program, to the plurality of OSs as main memories therefore, respectively. In responding to an I/O instruction issued by a running one of said plural OSs, an address of said main memory assigned to said running OS which participates in an I/Oo operation requested by said I/O instruction is determined without intervention of the control program, and the address is translated into an address of the main storage of the computer system without intervention of said control program. The I/O operation is then executed by using the address resulting from said address translation.

I/O execution method for a virtual machine system and system therefor

In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is '1', it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is '0' indicating that the interruption is not acceptable by the VM, the interruption conrol mask of the corresponding dedicated real interruption priority order is also '0' and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

A file control system for virtual machines capable of executing simultaneously a plurality of operating systems in a single computer system under control of a virtual machine monitor for controlling the operating systems, wherein interface means for file input/output operation are provided between the virtual machine monitor and the operating systems for allowing the virtual machine monitor to manage a plurality of files owned by the virtual machines.

Virtual machine file control system which translates block numbers into

An area boundary between a system common area and a job private area is set at any page boundary independently from a segment boundary, and for the segment (boundary segment) containing the area boundary, a page table is prepared for each virtual address space. Thus, virtual pages which are not used as the system common area in the bondary segment can be used by jobs as job private areas. The real page is fixedly allocated to the virtual page belonging to the system common area in the boundary segment. Thus, it is not necessary to simultaneously update page tables for the system common area. Those virtual pages may be subjects of dynamic allocation of the virtual storage.

Virtual storage system and method permitting setting of the boundary

In a logic simulation method for performing logic simulation of a logic circuit including a circuit with unknown internal logic, the circuit itself with the unknown internal logic is used. The internal status of the circuit is set at an objective status using the interrupt operation afforded by the circuit and thereafter, input signal value is applied to the circuit to obtain a resultant output. For other logic circuits without unknown internal logic, software logic simulation is performed. During such software logic simulation, the actual circuit with unknown internal logic is called.

Logic simulation

In a virtual machine system (VMS) capable of concurrently running at least one operating system (OS) under one real computer system and a control program (VMCP) for controlling the VMS, the object is to reduce the overhead produced for simulating VM I/Os by direct I/O execution. A VM information area of a real sub-channel control block has a status field in which a flag indicating that the sub-channel is dedicated or not is contained. When the flag is '0', it means that the sub-channel is dedicated to the VM and the sub-channel scheduling by the VMCP is not necessary. As a real interruption priority order is dedicated to a VM, only I/O interruption requests of the VM are queued into the real interruption request queue of that dedicated priority order, and the mixing of VMs in that real interruption priority order is avoided. When an interruption control mask of an interruption priority order of the OS on the VM is '0' indicating that the interruption is not acceptable by the VM, the interruption control mask of the corresponding dedicated real interruption priority order is also '0' and the hardware interruption does not take place. Accordingly, the interruption is retained by the hardware and the I/O interruption retention for the VM by the VMCP is avoided.

I/O Execution method for a virtual machine system and system therefor

A logic design automation system examines correspondence relationship among sublogics in intermediate gate-level logic (containing neither physical design information nor manually optimized logic design information) produced from updated functional-level logic and current gate-level logic (containing the above information) to identify corresponding sublogics and non-corresponding sublogics of the gate-level logics with reference to primary input/output signals and input/output gates. For the corresponding sublogics, the corresponding sublogics of the current gate-level logic are selected, and for the non-corresponding sublogics, the non-corresponding sublogics of the intermediate gate-level logic are selected. The selected sublogics are combined to synthesize updated gate-level logic which preserved therein the physical design information and the manually optimized logic design information for portions of the current gate-level logic which need not be modified.

Incremental logic synthesis method

In order to carry out address translation which can reduce an overhead of the VMCP to support a virtual storage, a flag indicating a common segment in the virtual machine and a system identifier are held in a TLB, and a VM identifier is held in a segment table origin stack. For the common segment, a current VM identifier is compared with the VM identifier in the segment table origin stack to determine validity of a TLB entry, and for a non-common segment, a system identifier read from the segment table origin stack is compared with the system identifier in the TLB entry to determine validity of the TLB entry.

Address translator

A programmable logic array circuit which assumes terms which are not implicants to be DON'T CARE terms, and which produces a logic function having decreased number of product terms; and which has a logic function which eliminates the terms that have been regarded to be DON'T CARE terms.

Programmable logic array circuit with a decreased number of product terms

In a memory hierarchy system having two or more hierarchy storages of different access speeds and programs and/or data to be loaded on the hierarchy storages, an activity information acquisition unit and a display unit are provided to present information regarding selection of programs and/or data to be loaded on a higher level in memory hierarchy, a unit is provided which automatically decides loading of the programs and/or data on the higher level and executes reallocation of the programs and/or data on the basis of the information, and a unit is provided which permits the user to change the loading by using a user command. The user can make full use of these units during execution of the memory hierarchy control. In an embodiment, priority for the programs and/or data to be loaded on the higher level is calculated and decided. The programs and/or data are written into the real storage in accordance with their priority to increase the real storage hit rate upon occurrence of a next request for loading.

Memory hierarchy control method with replacement based on request

A data processing system in which a scan-in operation is initiated to scan in data for giving rise to occurrence of pseudo-failure in response to an address coincidence signal representative of a pseudo-failure signal. A one-shot suppression pulse signal is issued for inhibiting temporarily operation execution during a time span between the scan-in and the occurrence of failure.

Data processing system

Growing community of inventors

Hachioji, Japan

Takashige Kubo