Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Nuvoton Technology Corporation Japan

Panasonic Semiconductor Solutions Co., Ltd.

Takashi Yui

Hiroaki Fujimoto

Takeshi Kawabata

Yoshinobu Kunitomo

Kiyomi Hagihara

Yoshiyuki Arai

Fumito Itou

Yasutake Yaguchi

Yoshiaki Takeoka

Toshitaka Akahoshi

Akihiko Nishio

Masaru Sasago

Yoshihiro Mori

Toshiyuki Fukuda

Nobuo Aoi

Hiroki Yamashita

Kazuhide Uriu

Takahiro Kumakawa

Katsuhiko Kawashima

Toshio Fujii

Teppei Iwase

Kouichi Yamauchi

Kazumi Watase

Yusuke Kanda

Kenji Yokoyama

Satoshi Kanai

Koichi Seko

Mutsuo Tsuji

Shouichi Kobayashi

Atsushi Saiki

Yukiko Haraguchi

Naofumi Koga

A power amplifier semiconductor device includes: a substrate; a semiconductor layer provided on the surface of the substrate and including a plurality of unit HEMTs; a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs; a terminal layer provided on the connection layer; a back electrode which is provided on the bottom surface of the substrate and whose potential is set to a source potential; and substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias. In plan view, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.

Power amplifier semiconductor device

A semiconductor module includes: a semiconductor element; a wiring substrate on which the semiconductor element is mounted; a heat dissipation substrate; a first metal material that bonds the wiring substrate and the heat dissipation substrate; and a second metal material that bonds the wiring substrate and the heat dissipation substrate and has a different melting point from the first metal material. Each of the following is at least partially bonded: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, the second metal material and the wiring substrate, the second metal material and the heat dissipation substrate, and the first metal material and the second metal material. Each of the following is bonded by alloying: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, and the first metal material and the second metal material.

Semiconductor module

A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.

Semiconductor module and method for manufacturing the same

A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.

Semiconductor device having stacked chips, a re-distribution layer, and penetration electrodes

A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.

Semiconductor device

A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.

Semiconductor device comprising an extended semiconductor chip having an extension

A semiconductor device includes a first semiconductor chip; an extension formed at a side surface of the first semiconductor chip; a connection terminal formed on the first semiconductor chip; a re-distribution part formed over the first semiconductor chip and the extension and including an interconnect connected to the connection terminal and an insulating layer covering the interconnect; and an electrode formed above the extension on a surface of the re-distribution part and connected to the interconnect at an opening of the insulating layer. The electrode is mainly made of a material having an elastic modulus higher than that of the interconnect. The electrode includes a bonding region where the electrode is bonded to the interconnect at the opening, and an outer region closer to an end part of the extension. The interconnect is formed so as not to continuously extend to a position right below the outer region.

A pad () is provided on a surface connecting a first substrate () of a lower layer module with an upper layer module, the pad is partially covered by an insulating film () to form an opening section () exposing the pad (), a first connection terminal () is formed on the lower surface of the first substrate () of the lower layer module, the planar shape of the opening section () is different from the planar shape of the first connection terminal (), the outer shape of the opening section () is larger than the first connection terminal (), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal () spreading in the opening section () is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.

Semiconductor module for stacking and stacked semiconductor module

A semiconductor device includes: a first semiconductor device including an interconnect substrate having a cavity structure and a semiconductor element mounted on a bottom part of the cavity structure; and a second semiconductor device provided on and connected to the first semiconductor device via connection terminals. A sealing material is provided between the first semiconductor device and the second semiconductor device. A sloped portion is formed, at a corner portion at which the bottom part and a side wall of the cavity structure in the first semiconductor device meets, to be sloped toward a center part of the cavity structure and have a tapered shape which becomes continuously wider in the direction from an upper part to a lower part.

A semiconductor device fabrication method includes: forming an elongated holein a wiring board plate along a perimeter lineof a plurality of wiring board regions defined over the wiring board plate with a connecting portion left unremoved at a corner of each of the wiring board regions; mounting semiconductor elements on the wiring board regions; and cutting the connecting portion using a punchto isolate the wiring board regions from the wiring board plate into wiring boards. Each of the wiring boards has a cut edge formed by the punch, the cut edge starting from an end of the elongated holeprovided on a first side of the perimeter lineand extending across part of the connecting portion inside the perimeter line, the cut edge being angled inward of the wiring board so as to slope downward from the end of the elongated hole

Semiconductor device with a wiring board having an angled linear part

A modified layerand an altered layerare formed outside a dicing point of a dicing areaThus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor elementand a semiconductor substrateand from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

Semiconductor wafer, method of manufacturing the same and semiconductor device

A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.

Stacked chip semiconductor device and method for manufacturing the same

A semiconductor device having a wiring substrate, a semiconductor element mounted on the wiring substrate via a heat sink, a wire electrically connecting the wiring substrate and the semiconductor element, the wiring substrate having through holes each connected to the wire or the heat sink, and external electrodes formed on a back surface of the wiring substrate and connected to the through holes. An insulating layer is formed between the heat sink and the semiconductor element, and the heat sink is divided into at least two sections. Hence, the back surface of the semiconductor element maintains an electrically disconnected state irrespective of the potential of the heat sink, and the heat dissipation design is allowed greater flexibility. Thus, the external electrodes connected to the heat sink via the through holes are connected to the mounting substrate wirings having satisfactory heat dissipation efficiency, allowing the heat of the semiconductor element to escape efficiently.

A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.

Growing community of inventors

Shiga, Japan

Takashi Yui