Sandisk Technologies Inc.

Takashi Yuda

Yuji Fukano

Ryousuke Itou

Hiroyuki Kamiya

Manabu Kakazu

Noriyuki Nagahata

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening. The memory opening fill structure includes a memory film and a vertical semiconductor channel. The memory film includes a tunneling dielectric layer, a charge storage layer that laterally surrounds the tunneling dielectric layer, a dielectric metal oxide blocking dielectric layer that laterally surrounds the charge storage layer and contacts the vertical semiconductor channel, and a silicon oxide blocking dielectric layer that laterally surrounds the dielectric metal oxide blocking dielectric layer and contacts the vertical semiconductor channel.

Three-dimensional NAND memory device with reduced reverse dipole effect and method for forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening extending through the alternating sack, and a memory opening fill structure located within the memory opening. The memory opening fill structure includes a pedestal channel portion, a memory film overlying the pedestal channel portion, a vertical semiconductor channel located inside the memory film, and a channel connection strap that extends through an opening of the memory film and contacting the pedestal channel portion and the vertical semiconductor channel. The channel connection strap has a topmost surface located below a horizontal plane including a top surface of the vertical semiconductor channel. The channel connection strap portion may be formed by a selective semiconductor growth from physically exposed semiconductor surfaces, and may provide enhanced electrical connection between the pedestal channel portion and the vertical semiconductor channel.

Three-dimensional memory device containing a channel connection strap and method for making the same

A three-dimensional memory device includes a vertical semiconductor channel surrounding a vertical dielectric core. Laterally extending dielectric pegs structurally support the vertical semiconductor channel and the vertical dielectric core. The vertical semiconductor channel may be a single crystalline semiconductor channel.

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Yokkaichi, Japan

Takashi Yuda