Fujitsu Corporation

Fujitsu Semiconductor Limited

Takashi Yoneda

Toshikatsu Hosono

Kenji Suzuki

Hiroyuki Yamamoto

Yoshio Inoue

Masuo Inui

Masaru Ito

Shigenori Ichinose

Tetsuo Kawano

Toru Osajima

Koji Banno

Satoru Yoshikawa

Takanori Nawa

Rieko Suzuki

Masahito Isoda

Makoto Wakita

Miyako Fujita

Koji Tsuneto

Rieko Toki

A method for efficiently extracting a variation distribution of a characteristic for a semiconductor integrated circuit. The method extracts a characteristic distribution of a semiconductor integrated circuit by performing a mathematical analysis using a polynomial expression based on a variation distribution of a process sensitivity parameter.

Method and apparatus for extracting characteristic of semiconductor integrated circuit

A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations. The method includes holding systematic variation tables for physical parameters dependent on the layout of the semiconductor integrated circuit among physical parameters related to characteristics of the semiconductor integrated circuit, analyzing a design layout pattern of the semiconductor integrated circuit and selecting tables corresponding to the plurality of physical devices, and generating a physical parameter distribution based on the selected tables.

Layout analysis method and apparatus for semiconductor integrated circuit

An LSI design method according to the present invention is to estimate a timing uncertainty in an early stage of design for each item of which an influence on timing is uncertain among respective items requiring consideration relating to establishment of timing; and define a timing margin in each design stage by using the timing uncertainty estimation result depending on whether or not an influence of the each item on timing has been determined, followed by proceeding with the design in the respective design stages accordingly. As such, according to the present invention, a timing uncertainty is estimated in an early stage of LSI design, followed by proceeding with the design by using the timing uncertainty as required.

LSI design method

OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program

In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Method of designing wiring for power sources in a semiconductor chip, and a computer product

In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared. When Rw is less than or equal to RwL (S YES), the waveform rounding at the next-stage circuit cell is judged to fall within a predetermined limit value.

Method of designing semiconductor integrated circuit device, and apparatus for designing the same

A method for designing a semiconductor device having a plurality of logic elements provided with a plurality of power supplies. First, a power supply type name is given to each power supply in accordance with the purpose of the power supply in each logic element. Each logic element is associated with the power supply type name of the power supply that is to be provided to the logic element. A power supply group is formed for each power supply. Specific information of each power supply group associating the power supply type name with supplied voltage is generated. Then, the power supply provided to each logic element is determined by allocating the power supply group to the logic element. The method simplifies designing the layout of a semiconductor device operated by multiple power supplies.

Method for designing semiconductor device

A method and apparatus for calculating circuit delay times efficiently arranges and stores data to reduce system memory requirements, which allows computers without large storage devices, such as conventional personal computers with limited hard disk space, to be used for testing preliminary device designs, Delay time ratio coefficient values representing a ratio of a delay time determined by values of dependency factors having a large correlation with one another to a predetermined reference delay time of a circuit element are stored in a coefficient table. The dependency factors include process condition, in use or operational temperature, and first and second operational supply voltages.

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Kasugai, Japan

Takashi Yoneda