Sony Corporation

Sony Semiconductor Solutions Corporation

Komatsu Electronic Metals Co., Ltd.

Nec Electronics Corporation

Sumco Techxiv Corporation

Takashi Yokoyama

Taku Umebayashi

Masanori Hosomi

Yutaka Higo

Shunichi Sukegawa

Yasuo Kanda

Mikio Oka

Tatsuya Usami

Nobutoshi Fujii

Hiroshi Hasegawa

Seiji Nagahara

Junsuke Tomioka

Hajime Yamagishi

Kozo Nakamura

Toshirou Kotooka

Nobuaki Hamanaka

Toshimichi Kubota

Toshiaki Saishoji

Kazutoshi Shiba

Hirotaka Nakajima

Shunsaku Tokito

Toshiaki Saishouji

Kouzou Nakamura

Kazuyoshi Sakatani

Shin Matsukuma

Toshiaka Saishoji

A semiconductor device according to an embodiment of the present disclosure includes: a first substrate provided with an active element; and a second substrate laminated with the first substrate and electrically coupled to the first substrate, in which the second substrate is provided with a first transistor configuring a logic circuit on a first surface and with a non-volatile memory element on a second surface opposite to the first surface.

Semiconductor device and method of manufacturing semiconductor device

A nonvolatile memory cell includes a resistance-change nonvolatile memory elementand a selection transistor TR. One end of the nonvolatile memory elementis connected to one source/drain regionA of the selection transistor TR and is connected to a write line WR. The other source/drain regionB of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory elementis connected to a bit line BL.

Nonvolatile memory cell, nonvolatile memory cell array, and information writing method of nonvolatile memory cell array

Provided is a semiconductor device having a structure suitable for higher integration. The semiconductor device includes a transistor that includes a gate section, a first diffusion layer, and a second diffusion layer. The semiconductor device further includes a first electrically-conductive section a second electrically-conductive section that is electrically insulated from the first electrically-conductive section, a first storage element that is located between the first diffusion layer and the first electrically-conductive section and is electrically coupled to each of the first diffusion layer and the first electrically-conductive section, and a second storage element that is located between the second diffusion layer and the second electrically-conductive section and is electrically coupled to each of the second diffusion layer and the second electrically-conductive section.

Semiconductor device and imaging unit

A semiconductor device according to an embodiment of the present technology, and the semiconductor device includes: a first substrate provided with a memory array; and a second substrate that is stacked with the first substrate, and is provided with a peripheral circuit that controls operation of the memory array.

Semiconductor device

A semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.

Semiconductor device, solid-state imaging device with tantalum oxide layer formed by diffusing a material of an electrode of necessity or a counter electrode

A volatile logic circuit has a storage node, and stores inputted information. A plurality of non-volatile elements are connected to the storage node of the volatile logic circuit through the same connection gate, and control lines for control for these non-volatile elements are connected to the respective non-volatile elements, every non-volatile element. A plurality of non-volatile elements are connected to the volatile logic circuit through the same connection gate in such a way, thereby enabling the yield to be enhanced.

Semiconductor device having a volatile element and a plurality of non-volatile elements

A semiconductor device including a semiconductor substrate having a first surface and a second surface that face each other, and having an element region and an isolation region, the element region including a transistor in the first surface, and the isolation region including an element isolation layer surrounding the element region; and a contact plug extending from the first surface to the second surface in the isolation region of the semiconductor substrate.

Semiconductor device with transistor in semiconductor substrate and insulated contact plug extending through the substrate

The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.

Memory cell structure, method of manufacturing a memory, and memory apparatus

A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

Semiconductor device and method of manufacturing same

A semiconductor device of the technology includes a first diffusion section (), a second diffusion section (), a channel section (), a gate section (), and a stress application section (, or). In a semiconductor layer () having a groove (A), the first diffusion section () is formed at or in the vicinity of a bottom of the groove (A), the second diffusion section () is formed at an upper end of the groove (A), and the channel section () is formed between the first diffusion section () and the second diffusion section (). The gate section () is buried in the groove (A) at a position opposing the channel section (). The stress application section (, or) applies one of compressive stress and tensile stress to the channel section () in a normal direction to the semiconductor layer ().

Semiconductor device, memory circuit, method of manufacturing semiconductor device

A semiconductor device including a semiconductor substrate with a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.

Semiconductor device structure useful for bulk transistor and method of manufacturing same

A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

Growing community of inventors

Kanagawa, Japan

Takashi Yokoyama