Kabushiki Kaisha Toshiba

Lapis Semiconductor Co., Ltd.

Nissan Motor Company Limited

Sumco Corporation

Sumitomo Electric Industries, Limited

Nippon Steel Corporation

Nippon Telegraph and Telephone Public Corporation

Nippon Steel Chemical Co., Ltd.

Takashi Yamada

Hajime Nagano

Tsutomu Sato

Ichiro Mizushima

Takeshi Hamamoto

Akihiro Nitayama

Shinichi Nitta

Hiroshi Takato

Tohru Ozaki

Fumio Horiguchi

Kazumasa Sunouchi

Shigeru Kawanaka

Yoshihisa Iwata

Takashi Ohsawa

Katsuhiko Hieda

Hisato Oyamatsu

Masami Aoki

Osamu Fujii

Tomoaki Shino

Yoshihiro Minami

Satoshi Inoue

Kazumi Inoh

Yuso Udo

Naoko Okabe

Akio Suzuki

Yohji Watanabe

Tsuneaki Fuse

Yutaka Ishibashi

Tetsuya Nakai

Makoto Yoshimi

Katsujiro Tanzawa

Hideaki Nii

Bong-Gyun Ko

Sadayuki Yoshitomi

Shintaro Hirakawa

Yutaka Murano

Naohiro Shoda

Yoshiaki Asao

Yusuke Kohyama

Kimiyoshi Nishizawa

Takeshi Kajiyama

Tatsuya Ohguro

Shinji Miyano

Hiroaki Yamada

Hiroki Nakamura

Kenji Kojima

Yoshiaki Ouchi

Yasuji Ishizuka

Atsushi Azuma

Mamoru Terauchi

Tadashi Takano

Hideharu Ehara

Hitomi Kawaguchiya

Yoshio Nakazawa

Ryusuke Hayashi

Satosi Inoue

Kouji Hasimoto

Yoshihide Yamada

In writing and reading data at a semiconductor storage device, control is carried out such that, at a time of a burst mode, in a case in which a value of a block address which is, from addresses assigned to a region of an internal address, an address for selecting a sense amplifier block from plural sense amplifier blocks, is a largest value, a first sense amplifier block and a second sense amplifier block are made to access different banks, and, in case in which the value of the block address is not the largest value, the first sense amplifier block and the second sense amplifier block are made to access a same bank of plural banks.

Semiconductor storage device for high-speed burst access

A semiconductor device has stored therein a plurality of bits of fixed data. The semiconductor device includes a plurality of memory elements that correspond, respectively, to the plurality of bits of the fixed data, and that acquire, store, and output the value of each bit received at an input terminal of each of the memory elements according to a timing signal. An initialization control unit feeds, to the plurality of memory elements, an initialization signal upon receipt of a fixed data setting signal, each of the plurality of memory elements being initialized to a state of storing a corresponding value represented by a bit of the fixed data according to the initialization signal.

Semiconductor device

A non-volatile semiconductor storage device including a first potential retention line configured to retain a potential corresponding to data read from the memory cell, a second potential retention line configured to retain a reference potential read from the memory cell in which the reference potential is written after the data is read out, a sense amplifier configured to amplify a difference between the potential retained by the first potential retention line and the reference potential for reading out the data from the memory cell, a first offset adjustment circuit connected to the first potential retention line, for adjusting an offset for the potential, a second offset adjustment circuit connected to the second potential retention line, and an offset command signal supply circuit configured to supply a first offset command signal to the first offset adjustment circuit so as to control the offset.

Non-volatile semiconductor storage device

A semiconductor memory according to the present invention includes a first discharge circuit for discharging electric charge stored in a pair of bit lines; a second discharge circuit for discharging electric charge stored in the pair of bit lines; and a control part for selectively executing a low-speed discharge mode for operating only the second discharge circuit of the first and second discharge circuits, a high-speed discharge mode for operating both of the first and second discharge circuits, and a stop mode for stopping both of the first and second discharge circuits.

Semiconductor memory device with fast and slow charge and discharge circuits

A semiconductor memory includes j&#xd7;k first memory cells, j upper bit lines, (&#xbd;)j sense amplifiers, j&#xd7;k lower first bit lines, k first word lines, k pairs of plate lines, each pair having first and second plate lines, each being connected to odd-numbered and even-numbered first memory cells of one of the k columns, a pair of discharge signal lines having a first discharge signal line and a second discharge signal line respectively connecting two of the j upper lines in each sense amplifier to a prescribed potential, j&#xd7;m second memory cells, j lower second bit lines, m second word lines, m third plate lines each connected to the j second memory cells of one of the m columns, and j shield lines each provided at positions respectively corresponding to the j upper bit lines, which are parallel to one another.

Semiconductor memory

An interface circuit includes at least one semiconductor logic gate and a latch circuit. The semiconductor logic gate configured to receive an input signal having a signal level changeable and outputs a logic gate signal which has a signal level becoming a low level when a signal level of the input signal is not less than a logic threshold value, alternatively has a signal level becoming a high level when a signal level of the input signal is less than the logic threshold value. The latch circuit fetches the logic gate signal as a first latch signal, while fetching a signal which is converted from the input signal and has a signal level varying between a second voltage and the ground potential, alternatively, the input signal as a second latch signal, to output the first interface output signal and the second interface output signal.

Interface circuit

This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a first dielectric film provided on the semiconductor substrate; two Fins provided on the first dielectric film and made of a semiconductor material; a second dielectric film provided on facing inner side surfaces among side surfaces of the two Fins; a third dielectric film provided on outer side surfaces among side surfaces of the two Fins; a gate electrode provided via the second dielectric film between the inner side surfaces of the two Fins; and a plate electrode provided via the third dielectric film on the outer side surfaces of the two Fins, wherein the two Fins, the gate electrode, and the plate electrode are included in one memory cell.

Semiconductor memory device and method of manufacturing the same

To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide filmon the surface of a substrateconstituted of single crystal silicon, oxygen ionsare implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide filminside the substrate. Further included is a step of forming a predetermined-depth concave portiondeeper than substrate surfaceserving as a bulk area on which the mask oxide film is formed on the substrate surfaceserving as an SOI area by forming a thermally grown oxide filmon the substrate surfaceserving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Method of manufacturing SOI substrate

To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide filmon the surface of a substrateconstituted of single crystal silicon, oxygen ionsare implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide filminside the substrate. Further included is a step of forming a predetermined-depth concave portiondeeper than substrate surfaceserving as a bulk area on which the mask oxide film is formed on the substrate surfaceserving as an SOI area by forming a thermally grown oxide filmon the substrate surfacea serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Method for manufacturing SOI substrate

A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer on the semiconductor substrate having a thickness less than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

Semiconductor device substrate including a single-crystalline layer and method of manufacturing semiconductor device substrate

A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Element formation substrate, method of manufacturing the same, and semiconductor device

A semiconductor optical device comprises a first conductive type III-V compound semiconductor layer, a second conductive type III-V compound semiconductor layer, and an active region. The first conductive type III-V compound semiconductor layer is provided on a substrate. The second conductive type III-V compound semiconductor layer is provided on the substrate. The active region is provided between the first conductive type III-V compound semiconductor layer and the second conductive type III-V compound semiconductor layer. The active region includes a III-V compound semiconductor layer. The III-V compound semiconductor layer contains nitrogen and arsenic as V-group element. The hydrogen concentration of the III-V compound semiconductor layer is greater than 6&#xd7;10cm. The III-V compound semiconductor layer of the active region is doped with n-type dopant.

Semiconductor optical device

A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer

A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.

Semiconductor device having epitaxial layer

Growing community of inventors

Ebina, Japan

Takashi Yamada