Fujitsu Corporation

Takashi Umegaki

Shigeo Tani

Shosaku Yamasaki

Hiroyuki Matsuo

Kazuo Takatsu

Yoshinori Nakamura

Akihiko Oka

Nobuyuki Nemoto

Mitsuhiro Kawaguchi

Toshiharu Sakai

Ryoji Azumi

Nobuo Iguchi

Hiroaki Mori

Koji Komatsu

Yoshimasa Itsuki

Toshikazu Ota

Miki Hagino

A line switching device includes multiple input ports to which signals are input and that include first input ports and second input ports different from the first input ports; multiple output ports that include given output ports; a branch unit that branches first signals input from the first input ports; and a switch that selectively outputs, among second signals input from the second input ports and branched signals branched from the first signals by the branch unit, signals that are to be switched to an output port among the given ports.

Line switching device

A transmission apparatus includes: an assigning unit to assign a number to a group of concatenation information of leading and dependent data which are multicast or broadcast; a retrieval unit to retrieve the concatenation information of the leading data corresponding to the dependent data, the leading and dependent data having the same number; a regeneration unit to regenerate concatenation information of the dependent data in accordance with the concatenation information of the leading data; a storage unit to store switch information of the leading data, the switch information representing a switch which switches output destinations of the leading and dependent data; an information retrieval unit to refer to the storage unit in accordance with leading data information included in the concatenation information of the dependent data so as to retrieve switch information of the dependent data; and a switching unit to switch the output destination of the dependent data.

Transmission apparatus and switching method

There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.

Clock device

A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.

Network apparatus that determines whether data is written into buffer based on detection of a memory error

An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.

Terminal relay device and relay method

An optical terminal system having self-monitoring function is disclosed, which includes a high-level group loopback section for internally looping back a serial electric signal, a low-level group loopback section for internally looping back a parallel electric signal, a self-loop section for connecting a receiver device and a transmitter device to loop an electric signal received by the receiver device directly to the transmitter device, and a self-monitoring controller for performing a self-monitoring test on respective components of the receiver device and transmitter device by using the self-loop section and either one of the high-level group loopback section and the low-level group loopback section. The optical terminal system can selfcheck the functions thereof through self-monitoring without depending on a network.

Optical terminal system having self-monitoring function

A disparity detection circuit used in a signal decoder which decodes a 4-bit signal into an original 2-bit main signal and 1-bit service signal, from which the 4-bit signal is coded according to a coding rule which stipulates that an original 2-bit main signal and 1-bit service signal should be coded into a 4-bit signal with 1 additional bit added and with pre-determined disparity carrying, determines whether the 4-bit signal conforms to the coding rule and detects the disparity of the 4-bit signal which is determined as conforming to the coding rule.

Growing community of inventors

Osaka, Japan

Takashi Umegaki