Yozan Corporation

Takashi Tomatsu

Changming Zhou

Guoliang Shou

Kunihiko Suzuki

Kazunori Motohashi

Jie Chen

Ying Chen

Xuping Zhou

Shengmin Lin

Gouliang Shou

Masataka Fukui

Xiaoxing Zhang

Matched filter bank

An analog to digital converter comprises a differential input portion that receives an input voltage and a reference voltage and has a first and second output terminals, a positive feedback portion connected to said first and second output terminals, a buffer if CMOSFETs connected at its input to the first output terminal, a second buffer connected at its input to the second output terminal, and a comparison circuit including a first switching portion connected between the first and second output terminals for connecting and disconnecting the first and second output terminals in response to a comparison clock signal. The comparison circuit is connected at its output to the first or second buffer. The input voltage and the reference voltage are compared when said switching portion changes from the connecting condition to the disconnecting condition in response to the comparison clock signal.

Analog to digital converter

A filter circuit comprises a plurality of sampling and holding circuits for sampling and holding analog input signal with a predetermined sampling period, a calculation circuit for multiplying each the analog input signal by a predetermined multiplier, and for summing the multiplication results. The sampling and holding circuits are controlled in an electrical power such that the electrical power is decreased when holding.

Filter circuit

An A/D converter having a plurality of thresholding circuits corresponding to bits of output digital data, each of which includes odd number of inverters serially connected from a first stage to a last stage. The first stage inverter of the thresholding circuits have thresholds equal to a weights of the bits. The inverters of the last stage are of thresholds different from those of the first stage.

A computational circuit for a multi-value addition comprising a parallel adder, an output adder, a quantizing portion and a logic conversion portion. Addition circuits in the above adders and thresholding circuits in the above quantizing portion consist of voltage-driven circuits including capacitive couplings.

Computational circuit

An inverting amplifying circuit for outputting an inversion of an input with good linearity, having an inverter circuit, a feedback capacitance, an input capacitance, a first refresh switch, a second refresh switch, a sleep switch, and a first cutoff switch. A sleep voltage is input through the sleep switch to the inverter circuit for minimizing the electrical power consumption. The sleep switch connects a terminal of the inverter circuit directly to ground when in a sleep mode. The first cut off switch is connected between an output of the inverter circuit and an output of the inverting amplifying circuit.

Inverting amplifying circuit

An stable inverted amplifying circuit includes an odd number of CMOS inverters and a feedback capacitance. Balancing resistances decrease the inverter open gain and limit the gain of the entire circuit. Serial capacitances act to prevent low-frequency oscillation. Oscillation-preventing circuits are also provided to reduce high-frequency oscillation. Sleep, refresh, and sleep-refresh switches are used to cancel residual loads and reduce power consumption.

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Tokyo, Japan

Takashi Tomatsu