Kabushiki Kaisha Toshiba

Takashi Togasaki

Hirokazu Ezawa

Tatsuo Migita

Tadashi Iijima

Masayuki Uchida

Takeshi Miyagi

Kazuhiro Ueda

Takayuki Masunaga

Hideo Nishiuchi

Soichi Yamashita

Naotake Watanabe

Satoru Asagiri

Yoshiyuki Shimizu

Michiko Ooishi

Hiroshi Yamada

Kazuhito Higuchi

Masahiro Miyata

Yuji Iseki

Kunio Yoshihara

Yasushi Shizuki

Hisashi Ito

Kentaro Suga

Koji Maruno

Satoru Hara

Satoshi Sayama

According to one embodiment, a semiconductor power converter includes first and second electrical conductors opposed to each other, first and second semiconductor elements joined to a first joint surface of the first electrical conductor, first and second convex electrical conductors joined to the first and second semiconductor elements, a junction joined to the first and second convex electrical conductors and a second joint surface of the second electrical conductor, power terminals, signal terminals, and an envelope sealing the constituent members. The envelope includes a flat bottom surface which extends perpendicular to the semiconductor elements and in which first and second bottom surfaces of the electrical conductors are exposed.

Semiconductor power converter and method of manufacturing the same

According to one embodiment, a semiconductor device includes a first electrical conductor, a second electrical conductor, first and second semiconductors between the first and second electrical conductors, a first power terminal, a second power terminal, a signal terminal, and an insulator which covers the components. The insulator includes a flat bottom surface in which the first and second electrical conductors are exposed, a ceiling surface, a first end surface, and a second end surface. The power terminals and the signal terminal extend outwardly from the first and second end surfaces, and the ceiling surface, respectively. The first end surface, the ceiling surface, and the second end surface are formed with a parting line.

Semiconductor device

An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.

Electronic component and method of connecting with multi-profile bumps

An aspect of one embodiment, there is provided an ultrasonic transducer including a plurality of oscillators, each of the oscillator having a convex portion, a printed wiring board provided to be opposed to the convex portion, an adhesive material including at least a portion of the convex portion, the adhesive material joining the oscillator and the printed wiring board, and a resin provided between the oscillator and the printed wiring board, the resin covering the convex portion and the adhesive material.

Ultrasonic transducer and fabricating the same

According to one embodiment, a semiconductor apparatus includes a semiconductor device, a heat spreader, a regulating unit, a containing unit, and a holding unit. The heat spreader is bonded to the semiconductor device with an interposed solder layer. The regulating unit is configured to regulate a dimension between the semiconductor device and the heat spreader. The containing unit is configured to contain melted solder in an interior of the containing unit. The holding unit is configured to allow melted solder held in an interior of the holding unit. The holding unit is configured to replenish the melted solder in the case where an amount of the melted solder contained in the containing unit is insufficient. The holding unit is configured to recover the melted solder in the case where the amount of the melted solder contained in the containing unit is excessive.

Semiconductor apparatus and method for manufacturing the same

An ultrasonic probe includes, a transducer, a substrate includes electrodes formed on a front surface and a back surface and electronic components, first flexible wire substrates connected in such a manner that a first end is connected to the transducer and a second end is connected to a electrode at a side of the front surface of the substrate, second flexible wire substrates connected in such a manner that a first end is connected to the transducer and a second end is connected to a electrode at a side of the back surface of the substrate, and a dummy materials including the same rigidity and thickness as those of the first flexible wire substrate is arranged at a space, adjacent to a electrode at the side of the front surface of the substrate, corresponding to the second end of the second flexible wire substrate.

Ultrasonic probe and method for manufacturing ultrasonic probe

A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Manufacturing method of semiconductor apparatus and semiconductor apparatus

According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.

Manufacturing method of semiconductor device and semiconductor device

For a suppressed breakage after a flip chip connection of a semiconductor device using a low-permittivity insulation film and a lead-free solder together, with an enhanced production yield, bump electrodes () are heated by a temperature profile having, after a heating up to a melting point of the bump electrodes () or more, a cooling in which a temperature within a range of 190 to 210&#xb0; C. is kept for an interval of time within a range of 3 to 15 minutes, and a condition is met, such that 1.4&#x3c;L/L&#x3c;1.6, where Lis a diameter of second electrode pads (), and Lis a diameter of first electrode pads ().

Semiconductor device and fabrication method thereof

A semiconductor device wherein a sealing resin is filled in a space between an interconnecting wiring board and a semiconductor chip after the semiconductor chip is flip chip-mounted on the wiring board in which at least a non-planar region consisting of a through hole, a concave portion or a convex portion, or a region exhibiting poor wettability to the sealing resin is formed on the surface of the wiring board or the semiconductor chip so as to provide a void in the sealed resin filled between the wiring board and the semiconductor chip for the purpose of minimizing any bad influence from the sealing resin on the interconnecting wirings or elements formed on the semiconductor chip.

Growing community of inventors

Yokohama, Japan

Takashi Togasaki