Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takashi Tatsumi

Junji Mori

Hiroki Sugano

A system-in-package (SiP) type semiconductor device has a test function capable of conducting a test singly on a memory chip directly from outside. When a mode signal included in a test signal input from an external connection terminal indicates a 'normal operation mode', a test circuit provided on a logic chip allows a logic circuit to use an access path (wiring) to a memory circuit. On the other hand, when the mode signal indicates a 'test mode', the test circuit uses the access path to access the memory circuit and conducts a test, an accelerated life test, or a multi-bit test, based on the content of the test signal input from the external connection terminal. The test circuit also conducts a built-in self-test.

System-in-package type semiconductor device

The semiconductor circuit includes a driver that is input with a signal, a driver that is input with a signal, and a driver of which input terminal is connected to output terminals of both the drivers, and of which output terminal is connected to input terminals of both the drivers.

Semiconductor circuit and semiconductor device

An integrated semiconductor device with a wafer-level burn-in circuit includes a test mode register and an access controller. The integrated semiconductor device is set at a voltage force mode by placing the test mode register at a test mode, and is forcedly supplied with prescribed voltages. The wafer-level burn-in is carried out by setting an access controller at a WLBI (wafer-level burn-in) mode with maintaining the test mode. After completing the wafer-level burn-in operation, the WLBI mode is released. Then, an external tester reads test data from a memory core in the test mode, and compares the test data with expected values. The integrated semiconductor device with a wafer-level burn-in circuit can solve a problem of a conventional integrated semiconductor device with a wafer-level burn-in circuit in that it cannot verify the function of the wafer-level burn-in circuit properly.

Integrated semiconductor device with wafer-level burn-in circuit and function decision method of wafer-level burn-in circuit

A memory test circuit having access control circuits ( and or and or and ) recognizes a first memory circuit ( ) and a second memory circuit ( ), as one continuous memory, incorporated in a semiconductor processing device based on addresses and control commands provided from an external device. The memory test circuit then executes a memory test operation for the first and second memory circuits ( and ) continuously.

Memory test circuit

A multiple power supply semiconductor device includes a first semiconductor circuit for transferring signals with a signal level of a first voltage, a second semiconductor circuit for transferring signals with a signal level of a second voltage lower than the first voltage, a level shifter for converting a level of an output signal from the second semiconductor circuit to a third voltage higher than the first voltage, and a circuit for further converting the level of the signal whose level is converted to the third voltage to the first voltage to be supplied to the first semiconductor circuit. This makes it possible to implement a multiple power supply semiconductor device with low power consumption and small hardware volume.

Low power consumption multiple power supply semiconductor device and signal level converting method thereof

A DRAM and a system LSI incorporating the DRAM. The DRAM has a self refresh address control section (11) inputs a control signal to optionally specify a period of a self refresh operation for the DRAM, a self refresh control circuit (7,71) for specifying the period of an address signal to be used for the self refresh operation and for outputting a self cycle signal, and a row address buffer (8) for providing addresses to the memory cell array (10) based on the self cycle signal as a trigger signal.

DRAM incorporating self refresh control circuit and system LSI including

A divider comprising a first and second normalizing circuits (5, 6) each which holds a hexadecimal-normalized mantissa data of a dividend and divisor respectively, a selector (7) which inputs the mantissa outputted from the first normalizing circuit (5), a remainder data outputted from a latch (13), a borrow signal (16) of a subtracter (8) which subtracts the mantissa data of the divisor from the mantissa of the dividend data of the remainder data, and control signals 21, 22, 23 respectively indicating a first, second and third and after third division cycles, through-outputs the mantissa data of the dividend in the first division cycle, shifts the mantissa data outputted from the first normalizing circuit (5) to the right by three bits and outputs it when the borrow signal (16) indicates '0' in the second division cycle, shifts the mantissa data outputted from the first normalizing circuit (5) to the left by one bit when the borrow signal (16) indicates '1', and through-outputs the remainder data outputted from the latch (13) in the third division cycle, and a dividing circuit. (100) which calculates a quotient data and a remainder data by using data outputted from the selector (7) and the mantissa data outputted from the second normalizing circuit (6).

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Tokyo, Japan

Takashi Tatsumi