Matsushita Electric Industrial Co., Ltd.

Nitto-denko Corporation

Panasonic Corporation

Takashi Taniguchi

Tamotsu Nishiyama

Naofumi Takagi

Akira Miyoshi

Hiroshige Hirano

Hisataka Ito

Shigeo Kuninobu

Tetsuya Tanaka

Kazuhiro Fuke

Tsuguyasu Hatsuda

Toru Kakiage

Miki Urano

Sadahito Misumi

Tatsumi Sumi

Toshitsugu Hosokawa

Hiroshi Noro

Shinya Ota

Kazuhiro Ikemura

Hideyuki Kabuo

Tsutomu Nishioka

Tadaaki Harada

Shinichi Ohizumi

Masao Gunji

Michiharu Shikata

Hisakazu Edamatsu

Chisato Goto

Seigou Takuwa

Minoru Yamane

Takamitsu Ota

Kazuhiko Yoshida

Yasushi Kannan

The present invention relates to a resin composition for forming an insulating resin layer for optical semiconductor element housing package having a concave portion in which a metal lead frame and an optical semiconductor element mounted thereon are housed, in which the resin composition includes the following ingredients (A) to (D), and the ingredients (C) and (D) are contained in a blend ratio (C)/(D) of 0.3 to 3.0 as a weight ratio thereof: (A) an epoxy resin; (B) an acid anhydride curing agent; (C) a white pigment; and (D) an inorganic filler.

Resin composition for optical semiconductor element housing package, and optical semiconductor light-emitting device obtained using the same

The present invention relates to a resin composition for optical semiconductor devices, the resin composition including the following ingredients (A) to (D): (A) an epoxy resin; (B) a curing agent; (C) a polyorganosiloxane; and (D) a white pigment.

Resin composition for optical semiconductor device, optical-semiconductor-device lead frame obtained using the same, and optical semiconductor device

A decryption process chip has a memory in which a first decryption control unit for decrypting a scramble key by using an ECM and an EMM is downloaded from outside and stored. A stream input unit extracts a packet including the ECM based on first information obtained from the first decryption control unit, and the first decryption control unit extracts the ECM from the packet. An STB control unit extracts only data including the EMM based on second information set up from the first decryption control unit, and the first decryption control unit extracts the EMM from the data. The stream input unit indirectly obtains a scramble key decrypted by the first decryption control unit so as to extract the scramble key and transmit it to a descrambler.

Digital video receiver, ECM extract equipment, EMM extract equipment, scramble key extract equipment, CCI extract equipment, digital video receiving system, ECM extract method, EMM extract method, scramble key extract method, CCI extract method, digital video receiving method, and recording medium

The present invention relates to an epoxy resin composition for optical semiconductor element encapsulation, the epoxy resin composition including following components (A) to (C): in which n is a positive number,

Epoxy resin composition for optical semiconductor element encapsulation and optical semiconductor device using the same

Semiconductor sealing epoxy resin composition and semiconductor device using the same

An apparatus uses a sticky digit in rounding an interim solution Yr into a final approximate solution Ye for an infinite precise solution Y, determined by a function F according to Y=F(X) with respect to digital data X. The apparatus includes a partial product generator receiving a multiplicand and a multiplier, at least one of which represents an interim solution Yr, for generating a plurality of partial products; a sign inversion generator for generating a sign inversion value, expressed in the same format as the partial products, from at least a lower part of a subtrahend to enable place matching, where the subtrahend represents the digital data X; an adder for adding the partial products and the sign inversion value; a detector which, in response to the addition result, detects whether the subtrahend or a product of the multiplicand and multiplier is greater; and a sticky digit generator for generating the sticky digit in response to the detection result.

Method and apparatus for performing floating point arithmetic operation

A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.

Pulse signal generator and redundancy selection signal generator

A method and an apparatus for cache lock control are designed for use with a cache memory. The cache memory has divided entries each for storing data and cache lock information. Updating of data in each of the entries of the cache memory is controlled in response to cache priority order information in each of the entries of the cache memory.

Method and apparatus for a cache memory with data priority order

A post-processing is executed on a mantissa M and an exponent E of a floating point binary number as a result of subtraction for example, thereby to obtain a mantissa m and an exponent e of the result of the post-processing. Therefore, an output (E-1) of a decrementer and an output (amount of cancelling of mantissa LSA) of an advancing 1 detecting circuit are entered into a minimum value selecting circuit. The minimum value selecting circuit is adapted to set a shift amount SH to (E-1) and a magnitude-relation judging signal CR to 1 when (E-1) is smaller than LSA (that is, when a denormalize processing is required). When (E-1) is not smaller than LSA (that is, when a normalize processing is required), SH is set to LSA and CR is set to 0. A left shifter is adapted to supply, as the mantissa m of the result, a value obtained by executing a left shift processing having a shift amount SH on the mantissa M. A selecting circuit is adapted to supply, as the exponent e of the result, 0 when CR is equal to 1, and an output (E-LSA) of a subtracting circuit when CR is equal to 0. This enables the denormalize processing of a floating point binary number to be executed at a high speed equivalent to that at which a normalize processing is executed.

Method of and apparatus for normalization of a floating point binary

In an arithmetic processor, second data are subtracted from first data to derive a first overflow signal. The sum of the second data and '1' is subtracted from the first data to derive another overflow signal. The magnitude relation between the first and second data derived is detected from the derived overflow signals.

Floating point processor with high speed rounding circuit

A method and apparatus for cache lock control are designed for use with a cache memory. The cache memory contains a number of data entries, each divided into segments for storing address information, data, and a cache lock bit, respectively. The cache lock bit, when set in a data entry, prevents updating the address and data in that data entry. An address translator is provided for converting virtual memory addresses to physical addresses. The address translator includes address entries which include at least one segment for storing cache lock information, and cache lock information is transferred from the address translator to the cache memory.

Cache lock information feeding system using an address translator

An approximate square root Ya of a given value X is derived by referring to a relation Y=X.sup.1/2 at an accuracy at which an error between the approximate square root Ya and an infinitely precise square root Y is smaller than a weight of a digit in a digit place which is lower by two digit places than a least significant digit place for a final square root. The approximate square root Ya is rounded to an interim square root Yr equal to one of possible interim square roots which is closest to the approximate square root Ya. A value Xr is derived from the interim square root Yr using a relation Xr=Yr2. A sticky digit S is set to 0, 1, or -1 in response to a relation between the values X and Xr. The sticky digit S is added to a digit place having an order immediately lower than a lowest order digit place of the interim square root Yr, and a result of the addition is rounded in a designated rounding mode to obtain the final square root.

A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.1 according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

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Osaka, Japan

Takashi Taniguchi