Nec Corporation

Takashi Takenaka

Seiya Shibata

Kazutoshi Wakabayashi

Akira Mukaiyama

Hiroaki Inoue

Satoru Ishii

Hideo Hasegawa

Shintaro Nakano

Eita Kobayashi

A network system includes multiple processing units (----) on each of which a desired virtual network function can be configured and a management apparatus that determines a communication path that connects the processing units so as to deploy a set of desired virtual network functions. At least one of the processing units includes a first communication interface that is connectable to any different processing unit and at least one second communication interface that is directly connectable to a predetermined different processing unit. The management apparatus determines the communication path for deploying the set of the desire virtual network functions, in accordance with respective connectable communication interfaces of the processing units.

Network system and management method and apparatus thereof

Provided is for reducing access latency. A high-level synthesis device includes feature quantity obtaining unit and implementation determination unit. Feature quantity obtaining unit obtains an access feature quantity including a feature quantity relating to communication between a plurality of modules by analyzing an access pattern in communication between the plurality of modules. Implementation determination unit determines an implementation method for communicating between the plurality of modules based on the obtained access feature quantity.

High-level synthesis device, high-level synthesis method, and program recording medium

Provided is an image processing device for performing noise removal in which a plurality of noise removal actions are combined while minimizing necessary resources. The image processing device is provided with: a first frequency separation unit for separating the input image by frequency into a first low-frequency component and a first high-frequency component containing a higher-frequency component than the first low-frequency component; a second frequency separation unit for separating the first low-frequency component into a second low-frequency component and a second high-frequency component containing a higher-frequency component than the second low-frequency component; a first image transform unit for performing noise removal on the second low-frequency component and the second high-frequency component and outputting the noise-removed image as a first transformed image; and a second image transform unit for performing noise removal on the first high-frequency component and the first transformed image with less resources being allocated than those allocated to the first image transform unit, and outputting the noise-removed image as a second transformed image.

Image processing device and image processing method

A computation device includes a data path element () including a function processing unit () that executes a computation specified in a function using input data included in an event () as an argument; and a control path element () that detects the event () by use of a return value (ret) of the function. The function processing unit () includes a data calculation unit () that executes a computation and outputs a first result (d); and a control comparison unit () that outputs, to the control path element (), a result of comparison between the input data and data for specifying the event (), as the return value (ret).

Computation device and computation execution method

Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Behavioral synthesis apparatus, method, and program having test bench generation function

Logic verification is performed based on correspondence information and compile information. The correspondence information specifies information on pairs of fragments of descriptions to be compared for equivalence in a behavioral level description written in a programming language and an RT level description obtained through behavioral synthesis and information on pairs of signals to be compared for each of the description pairs. The compile information includes mapping information between the behavioral level description and an object code. A logic cone extraction section extracts first logic cones from the object code through symbolic simulation by referencing the correspondence information and the compile information. The logic cone extraction section extracts second logic cones from the RT level description. A logic cone comparison section verifies equivalence between the first and second logic cones.

Logic verification and logic cone extraction technique

For deriving an RTL description through several steps from a behavioral description, a behavioral synthesis device outputs an associated relation between intermediate level descriptions subsequent to the respective steps and intermediate level descriptions prior to the respective steps. A model extracting device extracts a model capable of expressing a control structure based on a finite state machine and an update of a signal from the behavioral description, each of the intermediate level descriptions, and the RTL description, as a model corresponding to those descriptions. A signal value function extracting device extracts signal value functions from the model. A function equivalence comparing device checks the equivalence between signal value functions prior and subsequent to the steps of the behavioral synthesis device.

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Tokyo, Japan

Takashi Takenaka