Fuji Electric Co., Ltd.

Denso Corporation

Takashi Shiigi

Yasuyuki Hoshi

Yuichi Harada

Seiji Momota

Shoji Yamada

Hitoshi Abe

Koh Yoshikawa

Makoto Asai

Takeshi Fujii

Tetsutaro Imagawa

Masaki Koyama

Yuichi Onozawa

Masahito Otsuki

Atsushi Yoshida

Hiroki Wakimoto

Yasunori Agata

Kenichi Ishii

Toshiyuki Matsui

Ryouichi Kawano

Shin'ichi Nakamata

Dawei Cao

Hiromi Koyama

Akihiro Fukuchi

Tomonori Mori

Fukuchi Akihiro

Provided is a test method of a semiconductor device under test, the test method comprising: controlling the semiconductor device under test to an on state by inputting a control signal to the semiconductor device under test; and observing the semiconductor device under test at a time of controlling the semiconductor device under test in the on state to an off state and evaluating the semiconductor device under test, wherein the semiconductor device under test includes one semiconductor device under test or a plurality of semiconductor devices under test, and in the controlling to the on state, a length of an on-time for which the one semiconductor device under test or the plurality of semiconductor devices under test are set to the on state is adjusted based on a magnitude of a variation in a delay time of the control signal.

Test method

Between a source electrode () of a main device () and a current sensing electrode () of a current detection device (), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator () is larger than a product of the resistor and maximal current flowing through the current detection device () with reverse bias. A diffusion length of a p-body region () of the main device () is shorter than that of a p-body () of the current detection device (). A curvature radius at an end portion of the p-body region () of the main device () is smaller than that of the p-body () of the current detection device (). As a result, at the inverse bias, electric field at the end portion of the p-body region () of the main device () becomes stronger than that of the p-body region () of the current detection device (). Consequently, avalanche breakdown tends to occur earlier in the main devicethan the current detection device ().

Semiconductor device

A semiconductor device, including a substrate, and a deposit layer and a semiconductor layer formed sequentially on the substrate. The semiconductor layer has selectively disposed therein a first region, a second region and a contact region. A gate electrode is disposed on the first region and the semiconductor layer via a gate insulating film. A source electrode is formed in contact with the contact region and the second region. A drain electrode is disposed on the back surface of the substrate. The source electrode has a first titanium (Ti) film, and a titanium nitride (TiN) film, a second Ti film, and a metal film containing aluminum (Al) sequentially formed on the first Ti film. The source electrode may further include another TiN film, on which the first Ti film is formed.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder.

A main semiconductor element and a temperature sensing part are arranged on a single silicon carbide base. The main semiconductor element is a vertical MOSFET and the temperature sensing part is a horizontal diode. An anode region of the temperature sensing part and an n-type source region and a p-type contact region of the main semiconductor element are connected by wiring by an anode electrode on a front surface of the silicon carbide base. The temperature sensing part, when the main semiconductor element is ON, is forward biased by drift current flowing in the main semiconductor element. The temperature sensing part, for example, is a poly-silicon diode constituted by a p-type poly-silicon layer and an n-type poly-silicon layer arranged on the front surface of the silicon carbide base. With such configuration, a semiconductor device having high reliability may be provided.

A current sensing part that detects overcurrent of a main semiconductor element is arranged on a same silicon carbide base as the main semiconductor element. An isolating part is arranged between the main semiconductor element and the current sensing part. The isolating part has a function of suppressing interference of the main semiconductor element and the current sensing part at the silicon carbide base. The isolating part is constituted by a trench provided a predetermined depth from a front surface of the silicon carbide base. An insulating film is provided in the trench, along inner walls of the trench. A poly-silicon layer is provided on the insulating film. With such a configuration, decreases in breakdown voltage of the current sensing part may be prevented.

A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a first semiconductor layer, a first semiconductor region, a second semiconductor layer, a second semiconductor region, a third semiconductor region, a fourth semiconductor sub-region, a first electrode, a gate insulating film, a gate electrode, and second electrode. At a corner part of an active region in which a main current flows, a fifth semiconductor sub-region is provided. An impurity concentration of the fifth semiconductor sub-region is higher than an impurity concentration of the second semiconductor layer.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

On a front surface of an n-type SiC substrate becoming a drain region, an n-type drift layer, a p-type base layer, and an n-type source layer are sequentially formed by epitaxial growth. In the n-type source layer, the p-type contact region is selectively provided. A trench is provided penetrating the n-type source layer and the p-type base layer in the depth direction and reaching the n-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 &#x3bc;m or less. A depth of the trench is, for example, 1 &#x3bc;m or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.

A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 &#x3bc;m. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.

In a semiconductor device, an interlayer insulating film electrically insulating a gate electrode and a source electrode has a structure in which a BPSG film and a NSG film are sequentially stacked. Further, the interlayer insulating film has a structure in which the BPSG film, the NSG film, and a SiN film are sequentially stacked, or a structure in which the BPSG film, the SiN film, and the NSG film are sequentially stacked. Such a structure enables the reliability of the semiconductor device in which a pin-shaped electrode is bonded by solder to be improved.

A p-type base layer is selectively formed on a surface of an n-type drift layer; an n-type source layer is selectively formed on a surface of the p-type base layer; and a p-type contact layer is formed to be in contact with the selectively-formed n-type source layer. A p-type counter layer is formed to be in contact with the n-type source layer, so as to overlap the p-type contact layer, so as to be separated from an interface where the p-type base layer and the gate oxide film are in contact with each other, and to be shallower than the p-type base layer. Accordingly, switching destruction caused by process defects in an insulated gate semiconductor device is reduced.

Semiconductor device manufacturing method including a counter layer for power conversion

The semiconductor device includes a p-anode region disposed on an n-drift region, and a p-diffusion region disposed so as to be in contact with the p-anode region on the n-drift region. A resistance region disposed so as to be in contact with the p-diffusion region on an nregion, a plurality of p-guard ring regions, and a stopper region disposed away from the p-guard ring regions are provided. By providing the p-diffusion region, withdrawal of holes that concentrate to the p-anode region at the time of reverse recovery is suppressed, so that the semiconductor device has a high reverse recovery tolerance.

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Matsumoto, Japan

Takashi Shiigi