Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Takashi Sato

Takeshi Sakata

Yuichi Okuda

Yoshinobu Nakagome

Yoji Nishio

Hisashi Shiota

Satoshi Nakamura

Shigezumi Matsui

Motoo Suwa

Kazuyuki Sakata

Ryoichi Sano

Tsuyoshi Yaguchi

Kenzo Kuwabara

Koji Suso

Yukinobu Maruyama

Kazuaki Yoshida

Shigeki Tanaka

Atsushi Fujisawa

Junichi Takano

Kuninori Suzuki

Tokuo Naitou

Masakazu Sakano

Toshiyuki Shinya

Takafumi Konno

The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.

Semiconductor device and manufacturing method therefor

Illumination devices () and () which irradiate light having a wavelength of 1.1 &#x3bc;m or less are arranged on a front surface and a rear surface of a cover () of a dicing device (). After a wafer is placed on a dicing stage (), when the wafer is diced by a blade () attached to a spindle (), light is irradiated on an entire surface of an upper surface (element forming surface) of the wafer by the illumination devices () and (). At this time, an illuminance of light on the wafer is set at 70 lux or more and 2000 lux or less. By this means, during a dicing operation, an area to be a light-shielded area by the spindle () or the like is not present on the wafer.

Light illumination during wafer dicing to prevent aluminum corrosion

A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

Semiconductor integrated circuit

The present invention provides a data communication method and a data communication device capable of performing high-speed data communication by using a parallel link and higher-speed data communication by reducing a timing skew. A data communication method includes: a step of encoding data of N bits (N being 2 or larger) to transmission data of M bits (M being 3 or larger) on a transmission side; a step of generating a transmission signal in which transition takes place in at least one level of any of the transmission data synchronously with a transmission clock and transmitting the transmission signal to a transmission line on the transmission side; a step of recognizing transition in the signal of M bits received via the transmission line and detecting the reception data of M bits synchronized with the transmission clock on a reception side; and a step of decoding the reception data of M bits to the data of N bits.

Data communication method and data communication device and semiconductor device

Portable computer

A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival judging circuit for comparing phases of part or whole bits of data received from the parallel data wirings, and a timing adjusting mechanism for adjusting phases among parallel bits of the received data based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at a receiver.

Data transmitter

When there is a difference in the lengths of the passages among the parallel data wirings or a difference in the load capacitances inclusive of parasitic elements, a difference in the propagation time among the data becomes no longer negligible. At the time of transmitting data at high speeds in a short period, in particular, the setup time for receiving the data and the holding time are no longer maintained, and the data are not normally transmitted. In a data transmitter provided to address this problem, the receiver for receiving parallel data is provided with a simultaneous arrival judging circuit for comparing phases of part or whole bits of the received data, and with a timing adjusting mechanism for adjusting phases among the parallel bits at a point of receiving data in the receiver based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at the receiver. Even when there is a difference in the lengths of the paths or in the load capacities, therefore, the setup time for receiving data and the holding time are maintained.

Growing community of inventors

Koganei, Japan

Takashi Sato