Nec Electronics Corporation

Nec Corporation

Renesas Electronics Corporation

Takashi Sakoh

Takuya Kitamura

Hiroki Shirai

Mami Toda

Yoshihisa Matsubara

Naoki Kasai

Masayuki Hiroi

Ichiro Honma

Ryo Kubota

The present invention is directed to a semiconductor integrated circuit device that basically has a non-memory array area, a memory array area, and memory capacitors formed across lower embedded metal interconnection layers including a low-dielectric constant interlayer insulating film in the memory array area. In addition, a memory-periphery metal seal ring is provided in the lower embedded metal interconnection layers having at least the low-dielectric constant interlayer insulating film so as to surround the memory array area.

Memory and logic device and method for manufacturing the same

A semiconductor device, includes a substrate, an element isolating film formed in the substrate, a first element formation region isolated by the element isolating film, a second element formation region positioned adjacent to the first element formation region and isolated by the element isolating film, a first well of a second conductive type formed in a whole area of the first element formation region, a first transistor of a first conductive type formed on the first element formation region, a second transistor of the first conductive type which is formed on the first element formation region and whose threshold voltage is the same as a threshold voltage of the first transistor, a second well of the second conductive type formed in a whole area of the second element formation region, and a third transistor of the first conductive type formed on the second element formation region.

Method of manufacturing semiconductor device having plural transistors formed in well region and semiconductor device

A first transistor and a second transistor are formed in a first element formation region, and a third transistor is formed in a second element formation region. The three transistors are of the same conductive type, and the first transistor and the second transistor have the same threshold voltage. A first well is formed in the first element formation region by use of a first mask pattern, and a second well is formed in the second element formation region by use of a second mask pattern. A channel region of the first transistor and a channel region of the second transistor have a shape which is line-symmetrical with respect to a reference line. The first mask pattern has a shape which is line-symmetrical with respect to the reference line.

A semiconductor deviceincludes a first gate, which is formed using a gate last process. The first gateincludes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate electrode formed over the gate insulating film in the first concave portion; and a protective insulating filmformed on the gate electrode in the first concave portion. In addition, the semiconductor deviceincludes a contact, which is coupled to the N-type impurity-diffused regionin the both sides of the first gateand is buried in the second concave portion having a diameter that is large than the first concave portion.

Semiconductor device and process for manufacturing same

A semiconductor memory device comprises a comparing unit that comprises a potential of a memory cell with a reference potential supplied by a reference cell to read data of the memory cell; first and second bit lines connected to inputs of the comparing unit; a first memory cell connected to the first bit line; a second memory cell connected to the second bit line; a first reference cell acting as the reference cell; a second reference cell acting as another reference cell; a potential line that supplies the reference potential to the first and second reference cells; and a dummy cell comprising a coupling capacitor that stabilizes potential of the potential line.

Semiconductor memory device

A semiconductor memory device includes a sense amplifier, first and second bit lines connected to the sense amplifier, a first reference cell connected to the first bit line, and a second reference cell connected to the second bit line. A reference potential is simultaneously written to the first and second reference cells. Further, a dummy cell may be provided to be simultaneously, with the reference cell, with the reference potential.

Semiconductor memory device having memory cell and reference cell connected to same sense amplifier and method of reading data thereof

In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor deviceincludes a region Dfor forming an electric circuit, and a seal ring(guard ring) that surrounds the region Dfor forming the electric circuit. A DRAMis formed in the region Dfor forming the electric circuit. Interlayer insulating filmsandare formed on a semiconductor substrate. The seal ringis formed in the interlayer insulating filmsand, and at least a portion there of is located spaced apart from the semiconductor substrate

Semiconductor device and method for manufacturing same

The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell therein. DRAMhas word linesto, word linesand, memory cellstoand a reference cell. Gates of FETsin the memory cellstoare connected to the word linestorespectively. Gates of a FETand a FETin the reference cellare connected to the word linefor readout and the word linefor writing respectively. Here, potentials applied to the word linesandare lower than those applied to the word linesto.

A semiconductor memory device has bit lines, capacitors, bit contacts and capacitor contacts, wherein the bit lines are provided over a semiconductor substrate, the bit lines are connected to the semiconductor substrate through the bit contacts, the capacitors are connected to the semiconductor substrate through the capacitor contacts, and wherein in two adjacent bit lines, pitch d(first pitch) representing a pitch of portions provided with the capacitor contacts is larger than pitch d(second pitch) representing a pitch of portions provided with the bit contacts, and distance dbetween two such bit lines in the portions provided with the bit contacts is larger than width dof the bit lines in the portions provided with the bit contacts.

There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse residues each having the same patterns with those of the first terminal and the second terminal of the fuses, and configured so that patterns corresponded to the first terminals and the second terminals are electrically disconnected from each other.

Semiconductor chip and method of fabricating the same

When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiOfilm have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.

Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance

In a semiconductor device including a memory region and a logic region, one or more of a plurality of logic transistor connection plugs, buried in a first insulating layer and connected to a diffusion layer of a logic transistor, are left unconnected to a first interconnect provided in an upper layer.

Semiconductor device and method of manufacturing the same

A memory region including a capacitor element, a logic region including a logic circuit, and a boundary region located between the memory region and the logic region are provided on a silicon substrate. The memory region includes a plurality of memory transistors and memory transistor connection plugs. The boundary region includes a dummy contact plug in the same layer as the memory transistor connection plugs and logic transistor connection plugs. The upper face of the dummy contact plug is covered with a second insulating layer. An end portion of a capacitor layer and an upper electrode is located closer to an inner region of the memory region than the dummy contact plug is.

Semiconductor device

A semiconductor memory device comprises memory cells in rows and columns. Each memory is of the capacitor type and includes one portion of a dielectric layer. Antifuse-components are connected in series one after another between a power source electrode and an output terminal that is grounded when a MOS transistor is conductive.

Growing community of inventors

Kanagawa, Japan

Takashi Sakoh