Hitachi, Ltd.

Hitachi Electronics Engineering Co., Ltd.

Hitachi Haramachi Electronics Co., Ltd.

Takashi Saitoh

Shinichi Hayashi

Hitoshi Komuro

Hideho Yamamura

Shuroku Sakurada

Nobuya Niizaki

Sigeyasu Kouzuchi

A gate turn-off thyristor including: an n-type emitter semiconductor layer divided into a plurality of n-type areas; a p-type base semiconductor layer which cooperates with the n-type emitter semiconductor layer to form a first main circular surface; an n-type base semiconductor layer; and a p-type emitter semiconductor layer cooperating with the n-type base semiconductor layer to form a second main circular surface. An outer diameter of the p-type emitter semiconductor layer is smaller than that of the n-type emitter semiconductor layer. A first main electrode put in low resistance contact with the n-type emitter semiconductor layer is formed on the first main surface. A second main electrode put in low resistance contact with the p-type emitter layer and the n-type base semiconductor layer is formed on the second main surface. A control electrode is formed in the p-type base semiconductor on the first main surface. A first electrode plate larger in diameter than the n-type emitter semiconductor layer is connected electrically with the first main electrode. A second electrode plate larger in diameter than the n-type emitter semiconductor layer is connected electrically with the second main electrode.

Gate turn-off thyristor

The delay circuit of the present invention has a CR integrator including a variable capacitance diode. This CR integrator is arranged between the first and second comparators. By applying a constant DC comparison voltage to the other input terminal of the second comparator, delay amounts can be selectively changed for the leading and trailing edges of the pulse waveform.

Delay circuit including an improved CR integrator circuit

Growing community of inventors

Hitachiota, Japan

Takashi Saitoh