Megachips Corporation

Megachips Lsi Solutions Inc.

Other

Nintendo Co., Ltd.

Takashi Oshikiri

Tetsuo Furuichi

Takahiko Sugahara

Ikuo Yamaguchi

Takanobu Nakashima

Yasuyuki Kii

Kumiko Mito

An information processing system includes an information processing apparatus having a first function, and a server apparatus being configured to communicate with the information processing apparatus via a communication network. The information processing apparatus includes an operation control apparatus being configured to control the first function. The server apparatus transmits operation permission information indicating operation permission for the first function to the information processing apparatus, in response to satisfaction of a predetermined condition related to the information processing apparatus. The operation control apparatus activates the first function, in response to the operation permission information received by the information processing apparatus.

Information processing system

A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.

Memory control device, semiconductor memory device, memory system, and memory control method

An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate timing such as power-on, the information processing apparatus reads the stored data in which the error is found again on the basis of the error information stored in the nonvolatile memory, corrects the error and then rewrites the stored data into the flash memory. It is thereby possible to repair a recoverable bit error such as a read disturb. Therefore, a normal read operation can be performed without a hitch, and this can avoid giving any uncomfortable feeling to users.

Bit error repair method and information processing apparatus

A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.

Memory controller, memory control apparatus, memory device, memory information protection system, control method for memory control apparatus, and control method for memory device

When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory.

Memory system and computer system

A memory-specific tester has a buffer storing input pattern data and output expectation data. An address included in the input pattern data read from the buffer is sent to a semiconductor memory, and is then subjected to descrambling at a security circuit. The descrambled address is converted at an address conversion circuit to an address designating a region for storing a check pattern in a memory core. Data given from the memory core (check pattern) is subjected to scrambling at the security circuit, and is then sent to the memory-specific tester. The memory-specific tester makes comparison between expectation data and the data read from the semiconductor memory.

Semiconductor memory and method of testing semiconductor memory

An information processing apparatus causes an encryption key data generating section to generate key data stored in a semiconductor memory by using encryption key source data read from the semiconductor memory and cipher generation data stored therein, and stores the key data in a temporary storage section. The information processing apparatus transmits data encrypted by an encryption circuit by using the key data. Upon receipt of the encrypted data, the semiconductor memory executes a command decrypted by a decryption circuit similarly using the key data. This achieves data communication only between the predetermined semiconductor memory and the information processing apparatus.

Memory information protection system and methods

A semiconductor memory () comprises a controller () and a memory array (). The memory array () is controlled for each of block areas (. . . ). The information processing apparatus () can not generate a data erase command for each block area (). A data erase command () for a specified block area 'G' is encoded and stored in a block area 'A'. When a request for data erasing is issued, a CPU () of the information processing apparatus () reads an erase command () out from the semiconductor memory () and outputs the erase command () to the controller (). The controller () decodes the erase command () and performs a data erasing process for the block area &#x201c;G&#x201d;.

Semiconductor memory and information processing system

A memory is provided which simplifies the manufacturing process on the supplier side while satisfying specifications provided from the user side. An address space of a memory core includes an information storage region, a code region, and a no-write region. The information storage region includes a first region where no-write region information is written and a second region where a fixed value is written. Program code is written in the code region. The no-write region information indicates the position of the no-write region, and the fixed value indicates a fixed value that is intended to be written to the no-write region. The ROM selects between the fixed value and original read data that is obtained by a data selecting section directly from the memory core, and outputs the selected one as read data.

Storage device and data output circuit

While a semiconductor memory operates in a first operation mode with high security, an encrypted command is inputted and then decoded to acquire the first address information. After the semiconductor memory comes into a second operation mode where the level of security is lower than that of the first operation mode, a command is inputted. Then, the second address information is acquired from the command. A control circuit in the semiconductor memory generates an address of 10 bits by using the first address information as a high-order 4 bits and the second address information as a low-order 6 bits and outputs the address to a memory array. With this operation, it becomes possible to read/write data from/to the memory array.

Semiconductor memory and data access method

An object of the present invention is to provide a memory system that offers enhanced security of ROM code that is data whose contents can be utilized for a given purpose in its intact form. In a memory system, data is read from a memory according to at least two or more addresses outputted from an address generator, from individual pages uniquely specified respectively by the addresses. A data generator generates one piece of data on the basis of the at least two or more pieces of data read from the individual pages.

Memory system and data reading and generating method

The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.

Memory device

The present invention provides a semiconductor storage device that requires no specialized circuit or the like for reading redundancy data from a redundancy region, and that is capable of freely changing the arrangement of the redundancy region in the memory array area. A semiconductor storage device of the present invention includes a memory array configured as shown below. The memory array includes a user region which is composed of given page units and where user data is stored, and a redundancy region which is composed of the same given page units and where redundancy data is stored. The area in the memory array can be used either as the user region or as the redundancy region.

Growing community of inventors

Osaka, Japan

Takashi Oshikiri