Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electric Co., Ltd.

Takashi Ohtsuka

Kiyoyuki Morita

Michihito Ueda

Kenji Toyoda

Hideyuki Tanaka

Hiroaki Fujimoto

Kiyoshi Morimoto

Akihito Miyamoto

Takashi Nishikawa

Noboru Yamada

Takashi Nakabayashi

Tetsuo Kawakita

Kazuhiko Matsumura

Shinitsu Takehashi

Tomoyuki Komori

Hideyuki Arai

Atsushi Omote

Yuji Zenitani

Yoshiyuki Shibata

Shoji Miyake

An object of the present invention is to provide a fuel cell that operates in a temperature range of not lower than 100&#xb0; C., and a method for manufacturing such a fuel cell. The fuel cell of the present invention has a proton conductive gel, an anode electrode, and a cathode electrode,

Fuel cell in which proton conductive gel is used and manufacturing method thereof, and electric power generation method

A semiconductor device includes a capacitor formed by successively stacking a lower electrode, a capacitor dielectric film and an upper electrode on a substrate. The lower electrode includes a first conducting layer and a second conducting layer formed on the first conducting layer and having higher resistivity than the first conducting layer, and the capacitor dielectric film is formed so as to be in contact with the second conducting layer of the lower electrode.

Semiconductor device and method for fabricating the same

A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.

Semiconductor memory and method for manufacturing the same

A non-volatile memory comprising: a first substrate () and a second substrate (), the first substrate () having a plurality of switching elements () arranged in matrix, and a plurality of first electrodes () connected to the switching element (), the second substrate () having a conductive film (), and a recording layer () whose resistance value changes by application of an electric pulse, wherein the plurality of first electrodes () are integrally covered by the recording layer (), the recording layer () thereby being held between the plurality of first electrodes () and the conductive film (); the first substrate () further comprising a second electrode (), the second electrode () being electrically connected to the conductive film (), the voltage of which is maintained at a set level while applying current to the recording layer (). This non-volatile memory achieves high integration at low cost.

Non-volatile memory and the fabrication method

A non-volatile memory () which comprises an insulating substrate () having a plurality of first electrodes () extending therethrough from a front surface of the substrate to a rear surface thereof, a second electrode () formed on one surface side of the substrate (), and a recording layer () held between the first electrodes () and the second electrode () and variable in resistance value by electric pulses applied across the first electrodes () and the second electrode (), the plurality of first electrodes () being electrically connected to the recording layer () in a region constituting a single memory cell (MC). The non-volatile memory () can be reduced in power consumption and has great freedom of design and high reliability.

Non-volatile memory

A non-volatile flip flop according to the invention comprising: a flip flop section () having a pair of memory nodes () for storing a pair of inverse logic data elements; and a pair of non-volatile resistance change elements () which are connected to the pair of memory nodes () through switching elements () respectively and the resistances of which vary so as to be retainable, wherein, in a store operation, the resistances of the pair of non-volatile resistance change elements () can be varied according to the respective potentials of the pair of memory nodes () and, in a recall operation, the pair of memory nodes () can be placed at potentials respectively according to the difference in resistance between the pair of non-volatile resistance change elements ().

Non-volatile flip flop

This specification relates to a semiconductor device that comprises a semiconductor substrate, a source regionand a drain region, which are formed on the semiconductor substratewith a channel regiontherebetween; a floating gate electrodethat is formed on the channel regionwith a gate insulator filmtherebetween; a ferroelectric filmthat is formed on the floating gate electrode; and a control gate electrodethat is formed on the ferroelectric film, wherein intermediate insulator filmsandare formed between at least one of the pairs consisting of the floating gate electrodeand the ferroelectric film, and the ferroelectric filmand the control gate electrode, and the intermediate insulator filmsandare made of hafnium oxide that contains nitrogen atoms.

Semiconductor device

The present invention relates to a non-volatile memory comprising: a first electrode (); a second electrode (); and a phase-change recording medium () sandwiched between the first electrode () and the second electrode (), in which resistance value is varied by applying an electrical pulse across the first electrode () and the second electrode (), at least one of the first electrode () and the second electrode () contains as a main ingredient at least one member selected from the group consisting of ruthenium, rhodium and osmium, and the phase-change recording medium () is formed of a phase-change material that contains chalcogen(s). This non-volatile memory exhibits improved durability and reliability by preventing deterioration of property (i.e., mutual impurity diffusion between the electrode and the phase-change recording medium) caused by application of current.

Non-volatile memory and fabrication method thereof

A silicon oxide film, a Pt film, a Ti filmand a PZT filmare deposited in this order over a Si substrate. The Si substrateis placed in a chamberso that the PZT filmis irradiated with an EHF wave. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate

The present invention provides a method of driving a nonvolatile flip-flop circuit comprising the following steps of: a data hold step of holding an input data signal D utilizing polarization of a ferroelectric material of a ferroelectric gate transistor () when the data signal D is input while a first clocked inverter (), a second clocked inverter (), and a third switching element () are turned on and a first switching element (), a second switching element (), and a third clocked inverter () are turned off; and a data output step of outputting an output signal Q (&#x2212;Q) based on the held data signal D placing the first clocked inverter (), the second clocked inverter (), and the third switching element () in the OFF state and placing the first switching element (), the second switching element (), and the third clocked inverter () in the ON state so as to interrupt an input of a data signal and maintain a polarization state of the ferroelectric material of the ferroelectric gate transistor ().

Nonvolatile flip-flop circuit and method of driving the same

A non-volatile memory cell comprising a latch circuit () which comprises a first node () and a second node () and latches complementary data set in the first node () and the second node (), a first switching element () which connects the first node () and a first data input/output line (), a second switching element () which connects the second node () and a second data input/output line (), a first ferroelectric capacitor () which connects the second data input/output line () and the first node (), and a second ferroelectric capacitor () which connects the first data input/output line () and the second node ().

Non-volatile memory cell and a method of controlling the same

A ferroelectric gate device which comprises a ferroelectric capacitor (), a switching element () serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor () having a source, a drain and a gate, said ferroelectric capacitor () having an input terminal (IN) at one end, the other end of said ferroelectric capacitor () being connected to one end of said switching element (), the other end of said switching element () being connected to the gate of said field-effect transistor (), by applying a voltage to said input terminal, said switching element () serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor () comprises is applied to said ferroelectric capacitor (), and by applying a voltage to said input terminal, said switching element () serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor ().

Ferroelectric element and a ferroelectric gate device using the same

In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistoris connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistoris the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

A semiconductor device includes: a control-voltage supply unit; an MOS transistor including a gate electrodeand drain and source regionsand; a dielectric capacitor; and a resistor. The dielectric capacitorand the resistorare disposed in parallel and interposed between the gate electrodeand the control-voltage supply unit. With this structure, a charge is accumulated in each of an intermediate electrode of the dielectric capacitorand the gate electrodeupon the application of a voltage, thereby varying a threshold value of the MOS transistor. In this manner, the history of input signals can be stored as a variation in a drain current in the MOS transistor, thus allowing multilevel information to be held.

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Toyonaka, Japan

Takashi Ohtsuka