Fujitsu Corporation

Fujitsu Semiconductor Limited

Takashi Ohkawa

Yoshio Kajii

Tsuyoshi Yanai

Tamio Miyamura

A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.

Semiconductor memory device

A semiconductor memory circuit includes a plurality of programmable memory cells capable of being programmed by a predetermined current; a plurality of bit lines connected with memory cells, a plurality of current distributors corresponding to the bit lines for connecting selected bit lines to an output terminal based on selection signals and separating non-selected bit lines from the output terminal, and a plurality of switching circuits corresponding to the bit lines for connecting non-selected bit lines to a low level potential point based on the selection signals. The determination of the existence of the inter-cell leakage is carried out precisely and easily.

Semiconductor memory circuit having inspection circuit

A semiconductor memory device having a PROM with an output register has an initialize input terminal and a programmable initial data memory cell for each bit. When an initialize input signal is supplied to the initialize input terminal, the output register is cleared or present in accordance with the content of the initial data memory cell, whereby the reduction of adaptability caused by a decrease in input terminals can be prevented, a circuit arrangement can be simplified, and a high degree of integration and high-speed operation can be achieved.

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Kawasaki, Japan

Takashi Ohkawa