Hitachi, Ltd.

Hitachi Global Storage Technologies Japan, Ltd.

Other

Hitachi Microcomputer Engineering, Ltd.

Hitachi Video and Information System, Inc.

Akita Electronics Co., Ltd.

Takashi Nara

Ryutaro Horita

Takushi Nishiya

Motoyasu Tsunoda

Hitoshi Ogawa

Katsumi Yamamoto

Masatoshi Nishina

Hiroshi Kimura

Kenichi Hase

Hideyuki Yamakawa

Takatoshi Kato

Seiichi Mita

Terumi Takashi

Kunio Watanabe

Hiroshi Ide

Shoichi Miyazawa

Shintaro Suzumura

Yoshiteru Ishida

Yoichi Uehara

Nobuaki Nakai

Yukie Miyazawa, Legal Representative

Shoichi Miyazawa, Deceased

Hitoshi Watanabe

Tatsuya Hirai

Akira Uragami

Yoshiju Watanabe

Akihiko Hirano

Tsuguyoshi Hirooka

Katsumi Osaki

Kyoko Tsukano

Yasuhiro Kanzawa

Masaou Takahashi

Haruto Katsu

A signal processing device having a feature of analog-to-digital converting a burst signal has a feature of selecting data bus to notify a disk control deviceof a conversion result via an NRZ data bus. The disk control deviceincludes means for storing the result of the analog-to-digital conversion of said servo positional signal. The positional signal of a head of the disk device is digitalized in an R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

Disk device and method of generating signal representing head

A signal processing device for analog-to-digital converting a burst signal has a feature of selecting a data bus to notify a disk control device of a conversion result via an NRZ data bus. The disk control device stores the result of the analog-to-digital conversion of the servo positional signal. The positional signal of a head of the disk device is digitized in a R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

Apparatus for information recording and reproducing

A signal processing device for analog-to-digital converting a burst signal has a feature of selecting a data bus to notify a disk control device of a conversion result via an NRZ data bus. The disk control device stores the result of the analog-to-digital conversion of the servo positional signal. The positional signal of a head of the disk device is digitalized in a R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.

Data encoding method for digital data recording and data recording system using the same

A transconductance control circuit is composed of a replica transconductance amplifier and resistance, a reference voltage source, first selectors, a differential amplifier, a voltage-current translate circuit with characteristics equal to the transconductance amplifier which constitutes analog filters. A first switch of the first selectors is connectable for the reference voltage source, and every constant period is made to connect it using clocks at the reference voltage source. A second switch of second selectors is connectable for plural capacitors, and every constant period is made to connect it using clocks at the capacitors.

Time sharing analog filters control method and magnetic disk system

A signal processing device having a feature of analog-to-digital converting a burst signal has a feature of selecting a data bus to notify a disk control device of a conversion result via an NRZ data bus. The disk control device stores the result of the analog-to-digital conversion of the servo positional signal. The positional signal of a head of the disk device is digitalizes in a R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

Signal processing apparatus and a disk control apparatus, with head positioning control based on digitized servo data

A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

Digital signal decoding apparatus and a decoding method used therein

Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

Digital information signal reproducing circuit and digital information

A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.

Signal processing delay circuit

A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

System for reproducing high-density magnetic record data with viterbi

A voltage-controlled filter circuit has a cutoff frequency directly proportional to a ratio of two current values. The filter circuit comprises a variable conductance circuit having two bipolar junction input transistors supplied with an input voltage signal at the bases thereof and a first variable current source at each emitter thereof. The collectors supply the bases of a pair of differential transistors. A second variable current supply is coupled to common emitters of the pair of differential transistors. Externally supplied control signals set the two current values of the variable current sources. The filter circuit may be manufactured as a semiconductor integrated circuit device for signal processing for use in processing a recorded signal read from a recording medium. The recorded signal is supplied to a semiconductor integrated circuit for signal processing to remove unwanted signal and noise components. Specific unwanted signal components may be removed and noise components whose frequencies exceed a cutoff frequency of a low-pass filter provided in a semiconductor integrated circuit are removed.

Voltage-controlled filter circuit, a semiconductor integrated circuit

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Takasaki, Japan

Takashi Nara