Hitachi, Ltd.

Mitsubishi Electric Corporation

Hitachi Vantara Corporation

Jsr Corporation

Takashi Nagao

Tomohiro Yoshihara

Yuusaku Kiyota

Ryosuke Tatsumi

Naoya Okada

Kensuke Takeuchi

Akira Yamamoto

Kentaro Shimada

Sadahiro Sugimoto

Katsuhiko Omae

Masayuki Funakoshi

Kenichi Betsuno

Tomohiro Kawaguchi

Kazuki Matsugami

Masahiro Tsuruya

Yuto Kamo

Hideaki Monji

Takanobu Kajihara

Atsuki Fujita

Yuki Okabe

Yoshihiro Yoshii

Michinori Nishikawa

Nobuhiro Yokoi

Azusa Jin

Takamasa Sato

Takashi Sakaguchi

Kohei Tatara

Yoshikazu Miyamoto

Masaaki Hosouchi

Miho Kobayashi

Hiroka Ihara

Jun Miyashita

Norio Simozono

Yoshinori Oohira

Kensuke Narita

Taiki Miyaji

Hiroaki Tokuhisa

Norio Emi

Yosuke Katoh

Takeyuki Imadu

Masakazu Hamada

Ryosuke Takeshita

Yuki Nikaido

A storage system includes a controller and one or more storage devices, and the controller can compress data in different compression units, and collectively compresses data of one or a plurality of consecutive addresses in each compression unit of the different compression units. The controller receives write data, determines whether read of data stored in the one or more storage devices is necessary for compression of the write data by a first compression unit, determines compression of the write data in the first compression unit when read is not necessary, and determines compression in the first compression unit or compression in a second compression unit smaller than the first compression unit based on a remaining endurance of rewriting of the one or more storage devices when read is necessary.

Storage system

A storage device includes a processor and an accelerator configured to compress and decompress data. The processor receives first replacement write data for a part of a first logical address region to update first data in the first logical address region that has been compressed by basic compression unit. The processor instructs the accelerator to compress the first replacement write data by a size smaller than the basic compression unit. The accelerator compresses the first replacement write data by the smaller size. The processor merges not-to-be-replaced data in the first logical address region and the first replacement data that are decompressed by the accelerator to generate uncompressed data having a size of the basic compression unit. The processor instructs the accelerator to compress the uncompressed data by the basic compression unit.

Storage device

A storage system includes: a central processing unit; a main memory; first management information that associates a hash value of received data with an address in a volume; and an I/O processing package. The I/O processing package includes an I/O processor and an I/O memory. The I/O processor executes protocol processing. The I/O processor executes at least a part of search processing of an address associated with a hash value of first received data in the first management information. The central processing unit controls execution of deduplication processing of the first received data based on data of an address associated with the hash value of the first received data.

Enhanced data management in distributed storage systems using dynamic load-based allocation of search and deduplication processes

A data store volume (DSVOL) for a snapshot group which is a group of the PVOL and one or more SVOLs for the PVOL is a data storage region where data of which a storage destination is one volume (VOL) of the snapshot group and meta-information of the data are stored, and the meta-information is information including address mapping between a reference source address which is an address of a position of the data in the snapshot group and a reference destination address which is an address of a position of the data in the DSVOL. A process of a storage system increases the number of DSVOLs in the snapshot group when an input/output (I/O) load on the snapshot group exceeds a threshold.

Storage system and storage control method

The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.

Storage device and data processing method

A storage device manages data stored in a storage drive in a plurality of logical hierarchies. The plurality of logical hierarchies include a writing hierarchy above a hierarchy of a parity group including a plurality of storage drives. The storage device writes received host data in a free area in the writing hierarchy. In the data recovery process for replacing a failure storage drive with a new storage drive, the storage device executes the garbage collection process on a first logical area in the writing hierarchy associated with the first parity group including the failure storage drive. In the garbage collection process, valid data is selected from the first logical area and copied to a second logical area associated with a second parity group different from the first parity group.

Storage device and data recovery method by storage device

The electronic device includes: a substrate having an electronic circuit formed therein; a housing for housing the substrate; and a connector disposed on the substrate and serving as an interface between outside and inside of the housing. The substrate has a main circuit pattern portion that forms a main circuit and a frame ground pattern portion that forms a frame ground. The main circuit pattern portion and the frame ground pattern portion are disposed so as not to overlap each other on the substrate and in the substrate. A terminal of the connector is disposed in the frame ground pattern portion.

Electronic device and electric power steering apparatus having electronic device mounted thereto

Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.

Storage system and control method of storage system including a storage control unit that performs a data amount reduction processing and an accelerator

In a semiconductor device, on a heat dissipation portion of a lead frame opposite to a mounting portion on which a semiconductor element is mounted, a thin molding portion having a thickness of about 0.02 mm to 0.3 mm is formed by a second molding resin which is a high-heat-dissipation resin. A scale-like portion on which scale-shaped projections are consecutively formed is provided over both sides across a resin boundary portion of the heat dissipation portion. The scale-like portion reaches abutting surfaces of an upper die and a lower die of a mold used in a molding process. Thus, the same void inhibition effect as with an air vent is obtained.

Semiconductor device

The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

Storage system and control method thereof

A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.

Optimized communicaton in storage system

A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.

Storage system and input and output control method

A shared base plate includes a plurality of base portions to which a plurality of electronic components including semiconductor switching elements are to be mounted, and a terminal formed portion formed so as to extend from the base portion to the outer side. The terminal formed portion includes a discrimination terminal which is used as a terminal in one of a first semiconductor module and a second semiconductor module and which is not used as a terminal in the other one. If the discrimination terminal that is not used as a terminal is cut to be short, it becomes possible to easily discriminate the semiconductor module from another semiconductor module having the shared base plate by outer appearances.

Shared base plate and semiconductor module provided with same

A semiconductor module includes a semiconductor switching element, a multiple of bases, on at least one of which the semiconductor switching element is mounted, a molded resin that seals the semiconductor switching element and the multiple of bases, a multiple of terminals formed integrally with each one of the multiple of bases and provided extending from an outer periphery side face of the molded resin, and a recessed portion or a protruding portion having a depth or a height such that creepage distance between the multiple of terminals is secured, and formed so as to cross an interval between the multiple of terminals, in one portion of the outer periphery side face of the molded resin between the multiple of terminals.

Semiconductor module

Growing community of inventors

Tokyo, Japan

Takashi Nagao