Sony Group Corporation

Sony Corporation

Takashi Morie

Hakaru Tamukoh

Quan Wang

Masatoshi Yamaguchi

Yasushi Fujinami

Goki Iwamoto

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Pulse signals corresponding to input values are input to the plurality of input lines. The multiply-accumulate operation device includes a plurality of multiplication units that generates, on the basis of the pulse signals input to each of the plurality of input lines, charges corresponding to multiplication values obtained by multiplying the input values by weight values, and an output unit that outputs a multiply-accumulate signal representing a sum of the multiplication values by accumulating the charges corresponding to the multiplication values generated by each of the plurality of multiplication units. A value of at least one of the input value or the weight value is limited.

Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation system, and multiply-accumulate operation method

A multiply-accumulate operation device, circuit and method are disclosed. In on example, a multiply-accumulate operation device includes input lines, multiplication units, an accumulation unit, a charging unit, and an output unit. Pulse signals having pulse widths corresponding to input values are input to the input lines. The multiplication units generate, based on the pulse signals, charges corresponding to multiplication values obtained by multiplying the input values by weight values. The accumulation unit accumulates a sum of the charges corresponding to the multiplication values. The charging unit charges the accumulation unit at a charging speed associated with its accumulation state. The output unit outputs a multiply-accumulate signal representing a sum of the multiplication values by executing threshold determination using a threshold value associated with the accumulation state of the accumulation unit on a voltage held by the accumulation unit after the charging by the charging unit is started.

Multiply-accumulate operation device, multiply-accumulate operation circuit, multiply-accumulate operation system, and multiply-accumulate operation method

An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.

Arithmetic logic unit, multiply-accumulate operation device, multiply-accumulate operation circuit, and multiply-accumulate operation system

Electric charges depending on values of Nelectric signals and values of corresponding positive loads are held in first capture-and-storage circuitry. Electric charges having a size depending on values of (N&#x2212;N) electric signals and corresponding absolute values of negative loads are held in second capture-and-storage circuitry. A sum of Nmultiplied values obtained by multiplying each of the positive loads by each of the values of the Nelectric signals is calculated when a voltage held in the first capture-and-storage circuitry reaches a first threshold. A sum of (N&#x2212;N) multiplied values obtained by multiplying each of the absolute values by each of the values of the (N&#x2212;N) electric signals is calculated when a voltage held in the second capture-and-storage circuitry reaches a second threshold A sum of N multiplied values is obtained by subtracting the sum of (N&#x2212;N) multiplied values from the sum of Nmultiplied values.

Growing community of inventors

Fukuoka, Japan

Takashi Morie