Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Socionext Inc.

Panasonic Intellectual Property Management Co., Ltd.

Panasonic Cororation

Takashi Morie

Shiro Dosho

Shiro Sakiyama

Akinori Matsumoto

Kazuo Matsukawa

Yusuke Tokunaga

Hirokuni Fujiyama

Kouji Okamoto

Yosuke Mitani

Kazuaki Sogawa

Hitoshi Kobayashi

Hiroya Ueno

Takuji Miki

Hiroki Hayashi

Masaya Sumita

Masayoshi Kinoshita

Hiroyuki Nakahira

Yukihiro Sasagawa

Norihide Kinugasa

Naoshi Yanagisawa

Akira Kawabe

Masao Takayama

Akio Yokoyama

Koji Sushihara

Toshiaki Ozeki

Joji Hayashi

Masaomi Toyama

Katsumasa Hijikata

Yuji Yamada

Hideki Nishino

Fumiaki Senoue

Tomoyuki Katada

Kiyotaka Tanimoto

Masashi Uchida

Kunihiro Fujiyama

Shiro Doushoh

Itsuki Yoshida

A comparator circuit outputs first and second digital signals corresponding to differential signals to a flip-flop having a predetermined forbidden input combination. A converter circuit performs differential amplification for the differential signals and converts the resultant signals to first and second signals that are complementary digital signals. A logic circuit performs predetermined logical operation, and when the logical values of the first and second signals are different from each other, outputs the first and second digital signals corresponding to the logical values of the first and second signals, and when the logical values of the first and second signals are the same, outputs the first and second digital signals having a same value other than the predetermined forbidden input combination.

Comparator circuit and A/D converter

An integrator including: a resistive element connected to an input terminal; an operational amplifier configured to receive, through the resistive element, an input signal that has been supplied to the input terminal; and a voltage regulator circuit connected to an intermediate node between the resistive element and the operational amplifier. The voltage regulator circuit has a first current source connected to the intermediate node, and a switch connected between the intermediate node and the first current source and selectively turning ON or OFF.

Integrator, delta-sigma modulator, and communications device

This D/A converter includes a plurality of D/A converter elements, each comprising current sources configured to supply output currents to output nodes, and first switches configured to control the output currents. The output nodes are connected to a capacitor section having second switches and a capacitive load. The D/A converter further includes a switch control circuit configured to control the first switches responsive to digital signals, and also control the second switches in accordance with the control of the ON/OFF state of the first switches.

Current type D/A converter, delta sigma modulator, and communications device

In a successive approximation AD converter, a noise generator outputs the output of a &#x394;&#x3a3; modulator as a noise signal. A selector circuit can output the noise signal, in place of a digital signal for generating a comparison-target voltage for the next bit, to a capacitor element of a capacitance DAC. During sampling of an analog input voltage, the noise signal is supplied to the capacitance DAC via the selector circuit, and thereafter normal successive approximation operation is executed.

Successive approximation AD converter and noise generator

A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.

Reference voltage stabilizer circuit and integrated circuit including the same

A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time &#x394;&#x3a3; A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time &#x394;&#x3a3; A/D converters to feed back the digital signal to the digital filter.

Actuator driver

An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n&#x2212;1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n&#x2212;1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.

Integrator, resonator, and oversampling A/D converter

In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p&#xd7;q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Coupled ring oscillator and method for initializing the same

A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node.

Pulse synthesis circuit

A pipelined AD converter () includes a plurality of conversion stages (, . . . ). In each of the conversion stages, an analog-to-digital conversion circuit () converts an input voltage (Vin) from the preceding stage to a digital code (Dout). A digital-to-analog conversion circuit () converts the digital code obtained by the analog-to-digital conversion circuit to an intermediate voltage (Vda). A charge operation circuit () has: a capacitor section (C, C) for sampling the input voltage; and an amplifier section () for amplifying a mixed voltage of the input voltage sampled by the capacitor section and the intermediate voltage obtained by the digital-to-analog conversion circuit. The amplifier section () includes a plurality of op-amps (amp, amp, . . . ) having the same configuration and connected in parallel with each other.

Pipelined AD converter

A successive approximation type A-to-D converter includes a cyclic D-to-A converter (), a comparator () for comparing an analog value with an output value of the D-to-A converter (), and memory means () for sequentially storing an output value of the comparator () and supplying the stored value to the D-to-A converter () in a reverse order.

A-to-D converter

Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.

Level shifter

Each of n level shifters (LSto LS) includes an NMOS transistor (Mn) for receiving any one of n clock signals (Pto P) and a PMOS transistor (Mp) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp) included in each of the level shifters (LSto LS) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn) included in that level shifter is a phase amount X (0&#xb0;&#x3c;X&#x3c;180&#xb0;). The phase amounts X of the n level shifters (LSto LS) are equal to each other.

Multiphase level shift system

A current mirror circuitis formed to have a current ratio (a transistor size ratio) of 1:m. As well, respective pairs of nMOS transistors MN, MNand nMOS transistors MN, MNare formed to have a current ratio of:m. Two currents output from the current mirror circuitare each distributed to two. The distributed currents flowing in the nMOS transistors MN, MNare added and are then allowed to flow into one resistor R. Hence, for the resistor R, only one resistor in which current of double flows suffices when m=1, for example. This effortlessly reduces the necessary resistance to one fourth.

Reference current circuit, reference voltage circuit, and startup circuit

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Osaka, Japan

Takashi Morie