Kabushiki Kaisha Toshiba

Nikon Corporation

Fujitsu Corporation

Matsushita Electric Industrial Co., Ltd.

Xanavi Informatics Corporation

Fuji Photo Optical Co., Ltd.

Ushio Denki Kabushiki Kaisha

Nkk Corporation

Ikeda Bussan Co. Ltd.

Kabushiki Kaisha Nikon

Takashi Mori

Tomoharu Tanaka

Ken Takeuchi

Seiichi Aritome

Kenichi Imamiya

Riichiro Shirota

Kazuhiro Shimizu

Hideko Oodaira

Yoshihisa Iwata

Toru Tanzawa

Masaki Momodomi

Yoshiyuki Tanaka

Fumitaka Arai

Yasuo Itoh

Kazuhito Narita

Susumu Fujimura

Hideo Kato

Masamichi Asano

Yutaka Okamoto

Hiroto Nakai

Kaoru Tokushige

Hideko Odaira

Koji Sakui

Hiroshi Watanabe

Yuji Takeuchi

Toshitake Yaegashi

Osamu Tanitsu

Hideki Komatsuda

Keniti Imamiya

Junichi Miyamoto

Kazushige Kanda

Fujio Masuoka

Kinya Kato

Hirohisa Tanaka

Toshihiko Himeno

Takahiro Sakuraba

Noriaki Yamamoto

Takuo Koyanagi

Tatsuki Tsukada

Koichi Yaita

Tetsuo Takahashi

Yasuhiro Omura

Takehiro Hasegawa

Yuji Kudo

Yoshihisa Sugiura

Yasuyuki Morita

Akira Miyaji

Koichi Kawata

Shinichiro Aoki

Shigeru Hagiwara

Hideo Hirose

Akitoshi Mori

Toshihiko Ozawa

Taro Ogata

Kiyoto Mashima

Koji Hosono

Hiroshi Sukegawa

Tetsuo Endoh

Tamio Ikehashi

Ryouhei Kirisawa

Sumio Tanaka

Kazuya Ota

Takashi Nomura

Akikazu Tanimoto

Koichi Matsumoto

Kyoichi Suwa

Tsuneyuki Hagiwara

Atsushi Kaneko

Toshio Yamamura

Kazunori Ohuchi

Katsuhiko Murakami

Hiroyuki Hiraiwa

Tatsushi Igarashi

Takao Naito

Yukio Yasuda

Eiichi Konno

Masato Shibuya

Kazuya Kawamoto

Takeshi Shirai

Michio Yamashita

Tsuyoshi Naraki

Masaichi Murakami

Takeaki Sato

Katsuhiko Nishikawa

Kazuhisa Kanazawa

Tetsuo Kikuchi

Hideki Sonobe

Osamu Inoue

Kazuto Tanaka

Masanori Sugihara

Akiyasu Yamaguchi

Toshimitsu Kobayashi

Akira Kuwabara

Yoshihisa Nakagawa

Mikito Nakabayashi

Kenzo Kai

Haruo Ozawa

Keiichiro Sakato

Kazutaka Okimoto

Tsubasa Hashimoto

An illumination optical system which illuminates an illumination objective surface with a light from a light source. The illumination optical system includes a spatial light modulator which includes a plurality of optical elements arranged within a predetermined plane and controlled individually, and which forms a light intensity distribution in an illumination pupil of the illumination optical system; and a polarization unit which is arranged in a position optically conjugate with the predetermined plane, and which polarizes an incident light beam having a first and second partial light beams, coming into the polarization unit such that the first and second partial light beams have polarization states different from each other, and emits the polarized incident light beam as an outgoing light beam, wherein the polarization unit changes, in a cross section of the outgoing light beam, a ratio between a cross sectional areas of the first and second partial light beams.

Illumination optical system, exposure apparatus, device production method, and light polarization unit

An electronic apparatus includes a housing that houses an electronic component, and a first cover and a second cover that cover the housing, wherein the electronic component is oriented along and on an inner side of a first sidewall of the first cover, wherein a side surface of the electronic component that faces the first sidewall has a cut, wherein the first cover has a recess that is depressed from the first sidewall toward the inner side in such a manner as to conform to the cut, and wherein the first cover is fastened at the recess to the second cover with a fastening member.

Electronic apparatus

A heat dissipation device includes: a first plate with a first surface on which a first heat dissipation fin is formed; a second plate with a first surface on which a second heat dissipation fin is formed, and a heat conduction unit that passes through a first through-hole of the first plate and a second through-hole of the second plate.

Heat dissipation device, electronic device, and base station device

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Semiconductor memory device capable of realizing a chip with high operation reliability and high yield

A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Nonvolatile semiconductor memory

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data '0' can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Nonvolatile semiconductor memory device

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device

According to one of embodiments, a method and apparatus for reproducing video and audio changes a playback speed for video and a playback speed for audio independently of each other. To provide an apparatus and method for controlling the playback speeds shortly before a period in which the video and audio should better be played back at a normal-speed, thereby to reduce the strange feeling the user may have as the playback changes from the high-speed playback to the normal-speed playback, a video signal and an audio signal are first isolated from a content and then demodulated. A playback speed is set for the video signal modulated, and a playback speed is set for the audio signal modulated. The video signal and the audio signal, each set to a playback speed, are output.

Method and apparatus for reproducing video and audio

Growing community of inventors

Kawasaki, Japan

Takashi Mori