Fujitsu Corporation

Takashi Miyoshi

Takeshi Horie

Hirohide Sugahara

Jeffrey D Larson

Takeshi Shimizu

Takashi Shimizu

Rajeev Murgai

Yukihiro Nakagawa

Subodh M Reddy

Yasushi Umezawa

Yinghua Li

Mehdi B Tahoori

An information processing device includes a processor; and an offload circuit coupled to the processor via links, the offload circuit including: a first circuit that computes processes of applications, a second circuit that collects values indicating performance information of the links for flows corresponding to the processes of the applications and maximum values indicated in performance information and usable by the links, and a third circuit that determines a flow not satisfying requested performance information based on the values indicating the performance information of the links for the flows, selects a link to which the flow is to be allocated, based on the maximum values indicated in the performance information and usable by the links and values indicated in performance information and currently used by the links, and allocates the flow to the selected link.

Information processing device, information processing method, and computer-readable recording medium storing program

An apparatus for processing information includes: a processor configured to execute a program; a first programmable circuit into which a processing circuit that executes data processing in accordance with an instruction from the processor is programmed; and a router circuit coupled to the processor, the first programmable circuit, and a router circuit of other apparatus, wherein the router circuit of the apparatus is configured to execute a routing process of information transferred between the processor and the first programmable circuit or between the processor and a first programmable circuit of the other information processing apparatus.

Information processing device and system for suppressing degradation of processing performance of program, method for controlling information processing system, and non-transitory computer-readable storage medium

An apparatus includes a first-processor, and a programmable integrated circuit coupled to the first-processor; a second-processor, and a memory coupled to the second-processor, the second-processor being configured to access the first-processor; and a third-processor to manage the first-processor, wherein the first-processor is configured to write, to the rewritable-integrated circuit, a computation circuit to perform computation according to information from the second-processor, and an encryption circuit to generate encrypted data by encrypting a computation result computed by the computation circuit, by using an encryption key for the computation circuit, the third-processor is configured to manage the encryption key in association with the computation circuit and notify the second-processor of the encryption key for the computation circuit, and the second-processor is configured to read out the encrypted data from the memory for storing the encrypted data, and decrypt the read encrypted data by using the encryption key notified from the third-processor.

Information-processing system, information-processing apparatus, management apparatus, and processing method

An information processing device, includes: a reconfigurable integrated circuit that, by being loaded with code expressing a configuration of a circuit, functions as the circuit; a memory that stores information indicating that the code is loaded into the reconfigurable integrated circuit, and resource information indicating an unused region in which circuit generation is available inside the reconfigurable integrated circuit; and a processor that searches a translation lookaside buffer (TLB) in which a virtual address associated with the code is associated with a physical address of the memory, determines, when the virtual address hits in the TLB, that the code is loaded, and generates, when the virtual address does not hit in the TLB, the circuit expressed by the code in the unused region indicated by the resource information.

Information processing device, method, and non-transitory computer-readable recording medium storing information processing program for loading code into reconfigurable integrated circuit

A transceiving system includes: a transmitter; and a receiver coupled to the transmitter via optical transmission lines, the transmitter includes: a first processor configured to generate division data obtained by dividing data; a modulator configured to modulate wavelengths of transport lights, which transport the division data, based on setting information including a correspondence relationship between identification information identifying each of the optical transmission lines and wavelength information indicating a wavelength, and output lights, each of which is superimposed with the respective division data, to the optical transmission lines; and a second processor configured to transmit changed setting information, which is obtained by changing the setting information, to the receiver, and the receiver includes: a de-multiplexer configured to separate lights from the optical transmission lines into de-multiplexed lights of a wavelengths, based on the changed setting information; and a third processor configured to convert the de-multiplexed lights into division data.

Transceiving system, transmitter, receiver, and control method of transceiving system

A switch apparatus for connecting an arithmetic processing apparatus and a control apparatus that controls the processing apparatus to an I/O apparatus is disclosed, the switch apparatus includes: a switch unit that connects either the processing apparatus or the control apparatus to the I/O; a first input/output control unit that outputs a first command that is received from the processing apparatus to the I/O through the switch unit, receives a response from the I/O that is operated based on the first command, through the switch unit, and outputs the received response to the processing apparatus; and a second input/output control unit that outputs a second command that is received from the control apparatus, to the I/O through the switch unit, receives a test result of the I/O that is tested based on the second command, through the switch unit, and outputs the received test result to the control apparatus.

Switch device, information processing device, and control method of information processing device

An accelerator management device includes an accelerator link DB that stores an accelerator identifier in association with an application identifier. The accelerator management device includes the accelerator mounting information DB that stores the accelerator identifier of an accelerator mounted in a slot in association with each slot identifier used to identify each slot of an expansion I/O box. The accelerator management device specifies an accelerator identifier corresponding to an application by referring to the accelerator link DB when an execution request of an application is received from a host. The accelerator management device specifies a slot identifier corresponding to the specified accelerator identifier by referring to the accelerator mounting information DB. The accelerator management device assigns the slot that is identified through the slot identifier which is specified by the second specifying unit to the host.

Accelerator management device, accelerator management method, and input-output device

An information processing device includes: a data transferring unit configured to directly transfer data to a first memory area allocated to a virtual machine from an input/output device for controlling a data input/output to/from an external device by mutually translating between an address of the first memory area allocated to the virtual machine and an address of a second memory area that is a real memory of the first memory area; a detecting unit configured to detect the data directly transferred from the input/output device to the first memory area allocated to the virtual machine; a registering unit configured to generate update information about the first memory area changed using the detected data and to store the update information in a first storing unit when the detected data satisfies a predetermined condition; and an outputting unit configured to output the update information.

Information processing device

A switch apparatus capable of being coupled to a computer and a plurality of devices, the switch apparatus includes: a first bridge coupled to the computer; a second-bridge group coupled to the devices; and a controller for controlling the connection relationship between the first bridge and the second-bridge group, wherein the controller assigns physical identifiers having different bus identifiers to the plurality of devices, assigns logical identifiers to the devices in accordance with an identifier assigned to the first bridge in response to an instruction for reading connection states of the devices received from the computer when the computer is coupled to the first bridge, and converts a physical identifier and a logical identifier of a packet transmitted between the first bridge and the second-bridge group in accordance with the correspondence relationships between the physical identifiers and the logical identifiers.

Switch apparatus

A relay device includes: memories, each memory being operable to store at least a data pair formed of a MAC address and a port number; a search unit to search only amongst ones of the memories having valid data pairs when searching for a port number based upon a MAC address; a data moving unit to move valid data pairs to different locations within the plurality of memories in order to reduce a total number of memories, amongst the plurality thereof, having valid data pairs; and a power supply controller to selectively stop supplying power to ones of the memories storing only invalid data.

Relay device, MAC address search method

A switching circuit connected to an I/O device having a plurality of functions, the switching circuit comprising: a processing unit that includes tables, each of which corresponds to one of the function of the I/O device, when the processing unit receives a packet that instructs to add a function to the I/O device, configured to select the table that contains a bus number of a destination of the received packet, and configured to notify a number of the selected table; and a filter configured to change a function number of the destination of the received packet to the number of the table notified from the processing unit.

Switching circuit connected to an I/O device, and switching circuit connected to an I/O device control method

A network connection device includes a processor and a switch unit. The processor learns an address. The switch unit outputs a packet received from a first port out of a plurality of ports to a second port. The switch unit manages a table including an entry which includes an address, status data, and an identifier of a port. The switch unit generates a first entry including a first address included in a first packet received via a first port, status data indicating 'learning', and an identifier of the first port, in the absence of the first address in the table, and requests the processor to learn the first address. The switch unit withholds requesting the processor to learn a second address included in a second packet received via the first port, when the second address is included in a second entry along with status data indicating 'learning'.

Network connection device, switching circuit device, and method for learning address

A transmission information transfer apparatus for realizing the MAC VLAN function with low latency includes: a VLAN table memory that manages a VID and a VLAN membership; a VLAN cache which is a cache memory that manages a VLAN Cache Index and VLAN membership in association with one another; an FDB that manages the VID, DA, and output port information in association with one another and further manages the VID, SA, and VLAN Cache Index in association with one another; an extraction section that extracts the VID, DA, and SA included in an input packet; an FDB search section that acquires output port information associated with the VID and DA, as well as the VLAN Cache Index associated with the VID and SA; a table controller that acquires the VLAN membership associated with the VLAN Cache Index; and an output port determination section that determines an output port of a packet.

Transmission information transfer apparatus and method thereof

A transmission information transfer apparatus includes: an FDB that manages IP addresses in association with a plurality of respective input/output sections; an IP packet recognition section that determines whether input transmission information includes an IP address indicating the destination of the input transmission information; an FDB reference section and output port determination section that determine, in the case where the input transmission information includes an IP address, whether the IP address included in the input transmission information and predetermined IP address associated with any one of the plurality of input/output sections different from an input/output section coincides with one another; and an output port determination section that sets, in the case where it has been determined that the IP address included in the input transmission information as the destination of the input transmission information and the predetermined IP address coincides with one another, any one of the plurality of input/output sections.

Transmission information transfer apparatus and its method

A switch operating in a multistage switch network is provided. The switch includes a plurality of ports, a first processor for processing a source address and a destination address of a packet received by the plurality of ports, and a second processor for including a memory storing data of the packet, and for outputting, under the control of the first processor, the data of the packet stored on the memory, wherein the first processor calculates a hash value of the source addresses of the packet in accordance with a specific hash function, identifies a output port connected to a switch that corresponds to the hash value and is to learn the source address, and causes the second processor to output the data of the packet to the output port.

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Kawasaki, Japan

Takashi Miyoshi