Fujitsu Corporation

Takashi Mimura

Keiji Ikeda

Kouichiro Odani

Atsushi Yamada

Shigeru Kuroda

Masahisa Suzuki

Kohki Hikosaka

Satoshi Hiyamizu

Seishi Notomi

A first film made of SiGe is formed over a support substrate whose surface layer is made of Si. A gate electrode is formed over a partial area of the first film, and source and drain regions are formed in the surface layer of the support substrate on both sides of the gate electrode. The gate electrode and source and drain regions constitute a first field effect transistor. A first stressor internally containing compressive strain or tensile strain is formed over the first film on both sides of the gate electrode of the first field effect transistor. The first stressor forms strain in a channel region.

Semiconductor device with strain in channel region and its manufacture method

A field effect transistor having a gate, a source, and a drain formed from metallic materials is disclosed that is able to supply a high driving current. In the field effect transistor, a source region, a drain region and a gate electrode are formed from silicide or other metallic materials. The metallic materials are selected so that in an n-channel MISFET, the work function Wg of the gate electrode and the work function Wg of the source region satisfy the relation of Wg&#x3c;Ws, and in a p-channel MISFET, work functions of the gate electrode and the source region satisfy the relation of Wg&#x3e;Ws.

Field effect transistor and production method thereof

The semiconductor device comprises a semiconductor layerformed on an insulation layer, a gate electrodeformed on the semiconductor layer with a gate insulation filmformed therebetween, a source/drain regionformed on the semiconductor layer on both sides of the gate electrode, and a semiconductor regionburied in the insulation layerin a region below the gate electrode. The surface scattering of the carriers and phonon scattering can be prevented while suppressing the short channel effect. Resultantly the semiconductor device can have high mobility and high speed.

Semiconductor device and method for fabricating the same

The semiconductor device comprises a semiconductor layerformed on an insulation layer, a gate electrodeformed on the semiconductor layer with a gate insulation filmformed therebetween, a source/drain regionformed on the semiconductor layer on both sides of the gate electrode, and a semiconductor regionburied in the insulation layerin a region below the gate electrode.

Semiconductor device with high mobility and high speed

In a semiconductor heterojunction corresponding to the n-channel and p-channel, the present invention is to enable the selective carrier injection into each channel by employing a height difference of a Schottky barrier, &phgr; B, which is provided between a source/drain consisting of metal or semiconductor-intermetallic compound and a semiconductor film used for each channel of the semiconductor.

Semiconductor device and manufacturing method of the same

A magnetoresistive head is composed of a soft magnetic layer formed on a substrate, a magnetic isolation layer formed on the soft magnetic layer, a magnetoresistive layer formed on the magnetic isolation layer, and a magnetic domain controlling magnetic layer, which is made of an anti-ferromagnetic layer or a hard ferromagnetic layer having a magnetically nonactive thickness, for covering a sense region of the magnetoresistive layer. Accordingly, because the magnetic domain controlling magnetic layer grows on the magnetoresistive layer in succession to the growth of the magnetoresistive layer, there is no probability that a natural oxide is produced in a boundary region between the magnetoresistive layer and the magnetic domain controlling magnetic layer. Also, there is no probability that a film thickness of the magnetoresistive layer placed under the magnetic domain controlling magnetic layer changes. Therefore, an exchange coupling magnetic field of the magnetic domain controlling magnetic layer for the magnetoresistive layer can be stabilized, a Barkhausen noise can be suppressed, and a superior magnetoresistive effect characteristic can be stably obtained.

Magnetoresistive head, manufacturing method of the head and magnetic

A logic circuit comprising an inverter which includes a load element connected at its one end to a high-potential power supply, an enhancement type N-channel field-effect transistor having a Schottky gate, the transistor being connected at its drain to another end of the load element and at its source to a low-potential power supply, an input terminal, and a gate-current control unit having negative resistance characteristic, the unit being provided between the input terminal and a gate of the enhancement type N-channel field-effect transistor for controlling a gate current that flows through the enhancement type N-channel field-effect transistor.

Logic circuit with enhancement type FET and Schottky gate

An ohmic contact layer is provided between an n-GaAs/n-AlGaAs/undoped GaAs double-heterojunction structure and source/drain electrodes in a high electron mobility transistor. The ohmic contact layer comprises In.sub.x Ga.sub.1-x As or Ge. The ohmic contact layer has a function of considerably reducing a specific contact resistance of a barrier formed at an interface between the ohmic contact layer and the source and drain electrodes. Thereby, a nonalloyed ohmic contact is formed between the source and drain electrodes and source and drain regions formed in the undoped GaAs layer.

Compound semiconductor device having nonalloyed ohmic contacts

A semiconductor device has an emitter potential barrier, a collector potential barrier, a base between the emitter potential barrier and the collector potential barrier, an emitter in contact, through the emitter potential barrier, with the base, and a collector in contact, through the collector potential barrier, with the base. The base has a thin base width capable of generating discrete energy levels of monority carriers therein. Carriers which are minority carriers in the base can be transferred from the emitter via the discrete energy levels in the base to the collector by resonant tunneling at an ultra-high speed.

Resonant tunneling minority carrier transistor

A depletion type element under the category of heterojunction field effect element having an n-region arranged in contact with a two-dimensional electron gas. More specifically a very limited region of the upper surface of the heterojunction faces the bottom surface of a gate electrode, thereby realizing various advantages, e.g.; (1) electron mobility is increased; (2) the resistivity is decreased in the source and drain regions as well as in the regions connecting the source and drain regions and the region facing the gate electrode; (3) the power consumption is decreased; (4) the reproductivity is improved, and (5) the overall reliability is improved.

Heterojunction field effect device having an implanted region within a

A semiconductor device, e.g., a complementary circuit comprising an n-channel transistor (Q.sub.n) utilizing a two-dimensional electron gas and a p-channel transistor (Q.sub.p) utilizing a two-dimensional hole gas, comprises: a semi-insulating GaAs substrate; a channel layer of an i-type GaAs having n.sup.+ -type source and drain regions and p.sup.+ -type source and drain regions; a buffer layer of an i-type AlGaAs preventing carriers from passing therethrough; first and second control layers of GaAs or AlGaAs having n-type or p-type conductivity, these layers being epitaxially formed in sequence on the substrate by an MBE method or an MOCVD method; and metal electrodes formed on the first and second control layers, n.sup.+ -type regions and p.sup.+ -type regions.

Method of making complementary field effect transistors

The present invention is related to an improvement of a high-electron mobility transistor (HEMT) which has an undoped GaAs layer and an N-doped AlGaAs layer a heterojunction formed between the undoped GaAs layer and the N-doped AlGaAs layer, respectively a gate electrode on the N-doped AlGaAs layer, and an electron-storing layer formed in proximity to the heterojunction due to the difference in electron affinity between the undoped GaAs layer and the N-doped AlGaAs layer. The known HEMT has a disadvantage in that during the formation of the source and drain regions by means of, for example, thermal diffusion, the impurities of the N-doped AlGaAs layer may diffuse into the undoped GaAs layer through the heterojunction so that the mobility of the electrons in the electron-storing layer is lessened. This disadvantage is removed in the present invention by the provision of a conduction layer formed by the epitaxial growth of highly-doped GaAs. The known HEMT also has a disadvantage in that the source electrode or the drain electrode is electrically connected to the N-doped AlGaAs layer so that the electrons in this layer may lessen the mobility. This disadvantage is also eliminated in the present invention by the provision of an insulating layer. The heterojunction may be formed between Gallium Aluminum Arsenide and Gallium Arsenide, Gallium Aluminum Arsenide and Germanium, Gallium Arsenide and Germanium, Cadmium Telluride and Indium Antimonide, or Gallium Antimonide and Indium Arsenide.

HEMT with epitaxial narrow bandgap source/drain contacts isolated from

The present invention is an improvement in a normally off-type high electron mobility transistor (HEMT) having a first single crystalline semiconductor layer, such as an undoped GaAs layer, and a second single crystalline semiconductor layer, such as an N-doped AlGaAs layer, having an electron affinity different from that of the first single crystalline semiconductor layer. A heterojunction is formed between the first and second single crystalline semiconductor layers. An electron-storing layer is formed adjacent to the heterojunctions serving as a conduction channel having a quasi two-dimensional electron gas. The concentration of electron gas is controlled by a gate electrode. An additional semiconductor layer, such as an N-doped GaAs layer, is formed at a portion of the second single crystalline layer in the area adjacent to the gate electrode. The additional semiconductor layer can generate the quasi two-dimensional electron gas even when no such gas is generated under the crystal parameter of the first and second single crystalline semiconductor layers. This generation of the quasi two-dimensional electron gas ensures that the HEMT has good reproducibility in respect to normally off-type operation.

Semiconductor device and process for producing the same

A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate, a channel layer, an electron-supply layer, a third layer, a first etching-stoppable layer, a fifth layer, and a second etching-stoppable layer, which layers are formed in sequence on the substrate. An etching process for forming grooves of gate electrodes of the FETs comprises a first etching treatment removing the first etching-stoppable layer portion in the E-mode FET region and the second etching-stoppable layer portion in the D-mode FET region, and a second etching treatment removing the third layer portion in the E-mode FET region and the fifth layer portion and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CCl.sub.2 F.sub.2 etchant gas is adopted, since GaAs can be thereby rapidly etched as compared with AlGaAs used for the etching-stoppable layer material.

Method of producing enhancement mode and depletion mode FETs

MOlecular beam epitaxy (MBE) requires that the surface of a substrate on which a semiconductor layer is formed by MBE be clean. Physical etching damages the substrate, while usual chemical etching damages vacuum pumps and contaminates MBE apparatuses. Hydrogen plasma etching can clean a substrate without damaging a substrate and a vacuum pump and without contaminating an MBE apparatus. Further, by combining MBE with formation of a protective layer without breaking the vacuum used in MBE, diffusion of an impurity in the semiconductor layer formed by MBE can be greatly decreased during a subsequent high-temperature heat treatment.

Growing community of inventors

Kawasaki, Japan

Takashi Mimura