Fuji Photo Film Company, Limited

Innotech Corporation

Innovision Corporation

Innotech Corproation

Takashi Miida

Jun Hasegawa

Jin Murayama

Nozomu Ozaki

Kazuhiro Kawajiri

Ryuji Kondo

Yoshimitsu Kudoh

Hiroshi Iwabuchi

Kazuo Kawamura

Masatoshi Tabei

Kazukiyo Tamada

Tatsuya Hagiwara

Hideki Mutoh

Yasumasa Hasegawa

Isao Taniguchi

Takashi Kagechika

Kiyoshi Inoue

Shigenori Baba

Kunimitsu Kousaka

Hiedki Mutoh

Seishi Okamoto

Katsuo Kawamura

A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a P type silicon substrate, a control gate CG and a pair of electrically isolated floating gates. Plural projections are formed in the silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate extending in the row direction faces the projection and the floating gate FG, FGvia an insulation layer. The width Wof the floating gate FG, FGin the column direction is larger than the width Wof the control gate CG, so the floating gate FG, FGand the control gate CG can be manufactured without the self-align process.

Semiconductor memory and method for manufacturing the same

A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

Semiconductor memory and method of manufacturing the same

A cell transistor includes source/drain regions formed at a lower level than part of its channel region. A select transistor has a channel region and source/drain regions formed at substantially the same level as the source/drain regions of the cell transistor. One of the source/drain regions of the cell transistor and one of the source/drain regions of the select transistor are electrically interconnected to each other in substantially the same plane.

Semiconductor device and semiconductor memory using the same

A multiple-bit cell transistor includes a P type silicon substrate, a gate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Semiconductor memory having storage cells storing multiple bits and a method of manufacturing the same

Semiconductor decive and semiconductor memory using the same

Disclosed is a method of storing optically generated charges by an optical signal in a solid state imaging device, which is particularly a method of storing optically generated charges by an optical signal in a solid state imaging device using a MOS image sensor of a threshold voltage modulation type, which is used for a video camera, an electronic camera, an image input camera, a scanner, a facsimile or the like. The method comprises the steps of preparing a solid state imaging device having a unit pixel including a photo diodeand a MOSFET, the MOSFEThaving a carrier pocketfor storing optically generated charges generated in the photo diode, the carrier pocketbeing provided under a channel regionin the vicinity of a source region, transferring the optically generated charges to the carrier pocketand then storing them therein while maintaining the channel regionin an accumulation state such that the optically generated charges are not affected by interface levels in the channel region

Method of preventing transfer and storage of non-optically generated charges in solid state imaging device

A transistor includes p-type semiconductor () including a projection () having a pair of side walls () facing each other, a gate insulation layer (), a pair of n-type source/drain regions (BL, BL), tunnel insulation layers (), a pair of floating gates (FG, FG), inter-polycrystalline insulation layers, and a control gate (CG). The root portion of the projection (A), which virtually connects the source/drain regions (BL, BL) with a straight line, is higher in the concentration of the p-type impurity than the other portion. A delete voltage for deleting charges stored in the floating gate (FG) is applied between the control gate (CG) and the source/drain region (BL, BL), so that a delete current flows toward the control gate (CG) or the source/drain region (BL, BL), the charges stored being deleted.

Transistor and semiconductor memory using the same

A multiple-bit transistor includes P type semiconductor including a projection, a gate insulation layer, a pair of N type source/drain regions, tunnel insulation layers, a pair of floating gates, inter-polycrystalline insulation layers, and a control gate. The root portion of the projection, which is defined by a straight line virtually connecting the source/drain regions, is higher in the concentration of the P type impurity than the other portion. A potential difference for write-in is set up between the source/drain regions while a write voltage is applied to the control gate, thereby causing electrons to be ballistically injected into at least one of the floating gates.

Semiconductor memory having storage cells storing multiple bits and a method of driving the same

A multiple-bit cell transistor includes a P type silicon substrate, agate insulation layer, a pair of N type source/drain regions, a pair of tunnel insulation layers, and a pair of floating gates. The silicon substrate is formed with a projection while the floating gates each are positioned on one of opposite side walls of the projection. Inter-polycrystalline insulation layers each are formed on one of the floating gates. A control gate faces the top of the projection via the gate insulation layer. An N type region is formed on each side of the projection and contacts the source/drain region adjoining it. The cell transistor lowers a required write voltage, broadens a current window, and enhances resistance to inter-band tunneling.

Disclosed is a solid state imaging device, comprising a unit pixel including a photo diode and a MOS transistor for optical signal detection provided with a high-density buried layer for storing optically generated charges generated by light irradiation in the photo diode , a vertical scanning signal driving scanning circuit for outputting a scanning signal to a gate electrode , and a voltage boost scanning circuit for outputting a boosted voltage higher than a power source voltage to a source region . In this case, a boosted voltage is applied from the voltage boost scanning circuit to the source region , and the optically generated charges stored in the high-density buried layer are swept out from the high-density buried layer by a source voltage and a gate voltage risen by the boosted voltage.

Solid state imaging device and driving method thereof

A solid-state imaging device is provided, which is capable of increasing an S/N ratio while enhancing a dynamic range, when a photoelectric signal is converted into a digital signal. This solid-state imaging device comprises: a plurality of photoelectric conversion devices arrayed in rows and columns, each of the photoelectric conversion devices converting an optical signal into an electric signal and outputting a first signal voltage; a difference signal generation circuit provided for each column, for sequentially inputting the first signal voltage and a second signal voltage obtained by initializing the photoelectric conversion devices, thereafter converting the first signal voltage and the second signal voltage into charges, generating a difference signal therebetween, and then outputting the difference signal after adjusting a gain according to a level of the difference signal; and an analog/digital conversion circuit connected to the output of the difference signal generation circuit.

Changeable gain amplifier, solid-state imaging device and optical signal reading method

A solid state imaging device includes a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. The solid state imaging device includes a photo diode formed in a second semiconductor layer of opposite conductivity type in a first semiconductor layer of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer of the opposite conductivity type in a third semiconductor layer of one conductivity type adjacent to the photo diode. A carrier pocket is provided in the fourth semiconductor layer and a portion of the first semiconductor layer under the second semiconductor layer is thicker than that portion of the third semiconductor layer under the fourth semiconductor layer.

Solid state imaging device, method of manufacturing the same, and solid state imaging system

A first buried layer of one conductivity and a first well region of opposite conductivity are formed in a semiconductor layer using a first mask. A second mask is used to form a second buried layer and a second well region of the opposite conductivity and to introduce impurity of the one conductivity type into a surface of the second well to form a channel doped layer of the one conductivity. A high concentration buried layer of the opposite conductivity is formed by introducing opposite conductivity impurity into the second well region using a third mask. A gate insulating film is formed on the semiconductor layer by thermal oxidation. A source region and a drain region of the one conductivity type are formed on the surface of the second well region, on both sides of a gate electrode.

A sole state imaging device includes a photodetection diode and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In a method of making the device, a carrier pocket is formed in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Solid state imaging device, manufacturing method thereof, and solid state imaging apparatus

Disclosed is a solid state imaging device, comprising: a photodetection diode; and an insulated gate field effect transistor provided adjacent to the photodetection diode for optical signal detection. In this case, a carrier pocket is provided in a second well region, and an element isolation insulating film is formed to isolate adjacent unit pixels from each other. In addition, an element isolation region of an opposite conductivity type is formed to isolate a second semiconductor layer of one conductivity type in such a way as to include the lower surface of the element isolation insulating film and reach a first semiconductor layer.

Growing community of inventors

Kanagawa, Japan

Takashi Miida