Olympus Optical Company, Ltd.

Symetrix Corporation

Takashi Mihara

Larry D McMillan

Hiroyuki Yoshimori

Carlos Alberto Paz De Araujo

Hitoshi Watanabe

Michael C Scott

Joseph D Cuchiaro

Shuzo Hiraide

John W Gregory

Carlos P De Araujo

Hiroshi Nakano

Eiji Yamamoto

Hideo Adachi

Masataka Ito

An image processing apparatus assumes the characteristic of a virtual image sensing optical system, and applies a blur effect corresponding to an in-focus state to a captured image. An image input unit captures image information including distance information to each portion of an object to be photographed. A parameter input unit inputs a parameter from which the effective aperture and focal length of the assumed image sensing optical system can be derived. An in-focal pint position designation unit designates the in-focal pint position of the assumed image sensing optical system. A blur state calculation unit calculates a blur state from the distance information input by the image input unit, the in-focal pint position designated by the in-focal pint position designation unit, and the parameter input by the parameter input unit. An image processing unit applies the blur effect to the image input by the image input unit in correspondence with the blur state calculated by the blur state calculation unit.

Image processing system capable of applying good texture such as blur

A display and camera device for a videophone comprises a liquid crystal display for displaying a picture, a camera such as a CCD sensor or a CMOS sensor, a free-form surface prism, and a prism for guiding light to the camera. The free-form surface prism has a concave reflector for optically enlarging a picture displayed on the display. A beam splitter is provided on a bonded surface between the free-form surface prism and the prism. The beam splitter is designed to reflect some of light beams from the display toward the reflector and transmit some of light beams from the reflector. A camera-system optical path extending from the camera is aligned with a display-system optical path extending from the display within the free-form surface prism and the outside space.

Display and camera device for videophone and videophone apparatus

A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Prebaking the substrate and oxygen in the RTP and anneal is essential, except for high bismuth content precursors. Excess bismuth between 110% and 140% of stoichiometry and RTP temperature of 725.degree. C. is optimum. The film is formed in two layers, the first of which uses a stoichiometric precursor and the second of which uses an excess bismuth precursor. The electronic properties are so regularly dependent on process parameters and material composition, and such a wide variety of materials are possible, that electronic devices can be designed by selecting from a continuous record of the values of one or more electronic properties as a continuous function of the process parameters and material composition, and utilizing the selected process and material composition to make a device.

Process for fabricating layered superlattice materials and making

A ferroelectric memory having a thin ferroelectric film sandwiched between a pair of electrodes as a memory cell includes a first pulse generating circuit for applying a first pulse having a voltage Ve higher than a coercive voltage Vc of the thin ferroelectric film to the memory cell, thereby forming a polarized state in a first direction of two states of polarization, a second pulse generating circuit for applying to the memory cell a second pulse having a voltage Vw whose polarity is opposite to a polarity of the first pulse applied by the first pulse generating circuit, thereby forming a partially polarized state containing both domains having polarization in the first direction and domains having polarization in a second direction opposite to the first direction, and an analog recording unit for performing analog recording by controlling the partially polarized state by using the second pulse generated by the second pulse generating circuit.

Ferroelectric memory and recording device using the same

A method of fabricating a ferroelectric or layered superlattice DRAM compatible with conventional silicon CMOS technology. A MOSFET is formed on a silicon substrate. A thick layer of BPSG followed by a thin SOG layer overlies the MOSFET. A capacitor is formed by depositing a layer of platinum, annealing, depositing an intermediate layer comprising a ferroelectric or layer superlattice material, annealing, depositing a second layer of platinum, then patterning the capacitor. Another SOG layer is deposited, contact holes to the MOSFET and capacitor are partially opened, the SOG is annealed, the contact holes are completely opened, and a Pt/Ti/PtSi wiring layer is deposited.

Integrated circuit with layered superlattice material compound

A ferroelectric gate transistor has a structure in which n-type source and drain regions are formed on a p-type semiconductor, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a gate electrode is formed thereon. Memory information is erased by applying a voltage V.sub.g to the ferroelectric to cause poling in the first direction. The memory information is written by applying a voltage V.sub.W lower than a coercive voltage of the ferroelectric and having a polarity opposite to that of the voltage V.sub.g to the ferroelectric. The memory information is read out by applying a voltage V.sub.DR lower than the voltage V.sub.W and having a polarity opposite to that of the voltage V.sub.g to the drain to read a drain current I.sub.DS.

Method of driving ferroelectric gate transistor memory cell

A substrate is prebaked in an oxygen furnace. A thin film of layered superlattice oxide is formed on the substrate by a chemical vapor deposition process. The film is RTP baked to provide grains with a mixed phase of A-axis and C-axis orientation. The film may be treated by ion implantation prior to the RTP bake and oxygen furnace annealed after the RTP bake. An electrode is deposited on the layered superlattice thin film and then the film and electrode are oxygen furnace annealed.

Chemical vapor deposition process for fabricating layered superlattice

A plurality of electrical light-emitting surface light source elements are arranged in a matrix form on a semiconductor substrate. Each of the surface light source elements has a ferroelectric capacitor portion and an electrical light-emitting portion. The capacitor portion has a lower electrode formed on the substrate, a ferroelectric thin film formed on the lower electrode, and an upper electrode formed on the thin film with an electron emission hole. The light-emitting portion has a carrier acceleration/multiplication layer formed on the upper electrode by a semiconductor layer, a light-emitting layer formed on the acceleration/multiplication layer, and a transparent electrode formed on the light-emitting layer. A plurality of switching elements are formed on the substrate in correspondence with the surface light source elements. A voltage applied across the upper and lower electrodes of the capacitor portion of a corresponding one of the surface light source elements according to a drive signal selectively supplied to the switching elements is inverted. Electrons emitted from the electron emission hole by polarization reversal generated in the thin film are injected in the light-emitting portion through the acceleration/multiplication layer to cause the light-emitting portion to selectively emit light, thereby obtaining visible light through the transparent electrode.

Display system utilizing electron emission by polarization reversal of

The present invention comprises a compound cavity in which a vertical-cavity surface-emitting laser and external mirror are combined, and the change in intensity of a laser beam or in mirror loss is detected by the detection unit. The detection unit includes a photodetector for directly detecting a variation in intensity of a laser beam, and PN junction potential difference detecting device for detecting a variation in mirror loss created due to a relative displacement between the external mirror and the vertical-cavity surface-emitting laser, based on a change in carrier density within the surface-emitting laser. The phase of the laser beam returning from the external mirror is determined by a relative displacement between the external mirror and the vertical-cavity surface-emitting laser, and the laser beam output varies at a period of a displacement amount corresponding to 1/2 of the wavelength of the laser beam. Such a displacement amount is calculated by the counting device and the operation device.

Optical displacement sensor

An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.

Ferroelectric integrated circuit

A ferroelectric memory includes a constant voltage source, a capacitor having first and second electrodes, and a transistor having a gate. A switch alternately connects the gate of the transistor to the first electrode and the constant voltage source. In another embodiment, there are two ferroelectric transistors, and the first electrode of each capacitor is connected both to the gate of the transistor and to a voltage source external of the memory.

Memory with ferroelectric capacitor connectable to transistor gate

A non-volatile integrated circuit memory in which the memory cell includes a first transistor gate overlying a first channel region, a ferroelectric material overlying a second channel region, and a second transistor gate overlying a third channel region. The channel regions are connected in series, and preferably are contiguous portions of a single semiconducting channel. The firm channel is connected to a plate voltage that is 20% to 50% of the coercive voltage of the ferroelectric material. A sense amplifier is connected to the third channel region via a bit line. The rise of the bit line after reading a logic '1' state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.

Ferroelectric memory and non-volatile memory cell for same

An integrated circuit non-volatile, non-destructive read-out memory unit includes a ferroelectric capacitor having first and second electrodes, a capacitance Cf, and an area Af, and a transistor having a gate, a source and a drain forming a gate capacitor having an area Ag and a gate capacitance Cg, a gate overlap b, and a channel depth a, with the capacitor first electrode connected to the gate of the transistor. The ferroelectric material has a dielectric constant .epsilon.f and the gate insulator has a dielectric constant .epsilon.g. A source of a constant reference voltage is connectable to the first electrode. A bit line connects to the second electrode. In one embodiment the first electrode and gate are the same conductive member. In another embodiment the second electrode and the gate are the same conductive member and the first electrode is formed by extensions of the transistor source and drains underlying the gate, with the ferroelectric material between the source and drain extensions and the gate. The memory unit has the parametric relationships: Cf&lt;5.times.Cg, Af.ltoreq.2Ag, b.gtoreq.2a, and .epsilon.g.gtoreq..epsilon.f/8.

Ferroelectric non-volatile memory unit

A ferroelectric memory having a structure in which source and drain are formed on a semiconductor substrate, a ferroelectric thin film is formed on a channel region between the source and drain regions, and a ferroelectric gate transistor memory cell having a ferroelectric gate transistor structure including a gate electrode made of a conductive gate electrode, is arranged on the thin film. An X selection line (column) is connected to the gate of the memory cell, and a Y selection line (row line) is connected to the source and drain, or the column and row of the X and Y selection line are connected to the memory cell vice versa. The memory can be driven only by 1-transistor/1-cell without a pass gate transistor, and the data can be non-destructively read out by applying a voltage lower than the coercive voltage of the ferroelectric to the gate electrode, the source and drain.

Method of driving ferroelectric memory

A method and apparatus for programming ferroelectric memory cells which reduces polarizability fatigue effects of switching polarization of the ferroelectric devices associated with the memory cells such as ferroelectric capacitors and transistors. Alteration of the pulse width duty cycle associated with signals used to switch ferroelectric device polarization is shown to reduce polarizability fatigue of the ferroelectric material thereby increasing the useful life of ferroelectric memory cells. Methods and apparatus for producing a signal pulse duty cycle in the range 2-30% is disclosed and shown to improve the useful life of the ferroelectric material.

Growing community of inventors

Saitama, Japan

Takashi Mihara