Megachips Corporation

Megachips Lsi Solutions Inc.

Nitto-Denko Corporation

Takashi Matsutani

Gen Sasaki

Shigenori Motooka

Hideo Sugawara

Ikuo Kawamoto

Yuki Haraguchi

Motoki Haishi

Motoyasu Tanaka

Nobuhiro Minami

Yusuke Nara

Nobuyuki Kozonoi

Keishi Kajiwara

Satoru Kubota

Kazuya Morimoto

Masayasu Yamamoto

Koji Ishio

An information reception device is provided with: operation surface which is adjusted to produce a characteristic index vibration by an object contact; a storage device stores candidate information (candidate information is related with the index vibration) which serves as a candidate of input information; a microphone which acquires observation information according to observation of the actual vibration arising in the surrounding environment; and a CPU. The CPU (selecting part) judges whether or not the index vibration exists in the observation information acquired. When the CPU judges that the index vibration exists, the CPU selects the candidate information which is related with the index vibration as the input information.

Information reception system, recording medium, and information input method

A PLC/power-supply hybrid device includes a power supply circuit. The power supply circuit includes a switching part for chopping a voltage of a voltage input terminal side, and a control circuit that controls the chopping by controlling switching of the switching part. The control circuit is operated in a normal mode and a transmission mode. The normal mode is a mode in which voltage conversion is performed. The transmission mode is a mode in which data transmission is performed through PLC using a power line that leads to the voltage input terminal. In the transmission mode, the control circuit modulates the switching of the switching part in accordance with transmission data.

PLC/power-supply hybrid device and device with communication function

A communication device includes: a first communication element configured to perform communication in a first communication scheme; a second communication element configured to perform communication in a second communication scheme different from the first communication scheme by using, as common hardware, at least part among hardware that implements the communication in the first communication scheme; a schedule management section that manages which of the first communication element and the second communication element is to be used; and a sequence control section that, in accordance with an instruction given from the schedule management section, sets the common hardware so as to enable the communication in the first communication scheme or the communication in the second communication scheme to be performed.

Communication device and method for operating communication device

A communication system includes information acquisition devices having facility information and an information collection device for collecting the facility information from the information acquisition devices. The information collection device requests the information acquisition devices to send the facility information by using the first communication unit and the second communication unit of the information collection device. Each of the information acquisition devices includes a communication scheme specifying section for specifying which one of the first communication unit and the second communication unit in each of the information acquisition devices has first received the request to send from the information collection device, and a communication control section for making a reply to the request to send by using the communication unit specified by the communication scheme specifying section.

Communication system, and communication device

A communication device includes: a reception element for receiving a radio signal modulated in a first modulation scheme or a second modulation scheme; a first demodulation element for demodulating the received radio signal in a first demodulation scheme corresponding to the first modulation scheme; a second demodulation element for demodulating the received radio signal in a second demodulation scheme corresponding to the second modulation scheme; and a modulation scheme detection section for detecting a modulation scheme of the received radio signal. The received radio signal includes modulation scheme determination information. The modulation scheme detection section detects the modulation scheme of the received radio signal based on a result of demodulation of the modulation scheme determination information performed by the first demodulation element and a result of demodulation of the modulation scheme determination information performed by the second demodulation element.

Communication device and communication system

A communication system includes a first communication apparatus and a second communication apparatus. The first communication apparatus generates and transmits communication data in accordance with a predetermined protocol. The second communication apparatus includes a power circuit section having a switching regulator, and is configured to receive the communication data transmitted from the first communication apparatus. The predetermined protocol includes a protocol defining that at least one portion of a bit sequence constituting the communication data should be associated with an operation of the switching regulator. The second communication apparatus causes the switching regulator to operate in a time period in which the at least one portion of the communication data is received, in a state where the communication data is received.

Communication system, communication apparatus, and communication integrated circuit

A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

DRAM controller that forces a refresh after a failed refresh request

A bank controller, an information processing device, an imaging device, and a control method are provided which enable improved data communication processing between FIFO memories of processing blocks and a synchronous DRAM. An arbiter determines the order of priorities in data communication performed between FIFO memories and associated banks. A precharge period detecting block detects the states of precharge of the banks. A register stores data required to determine the order of priorities (data indicating whether the banks are in a precharge period, data indicating whether data communication request signals are presented). This enables the arbiter to exclude FIFO memories that are associated with banks that are not allowed to perform data communication. Efficient data communication is thus implemented between the FIFO memories and the synchronous DRAM.

Bank controller, information processing device, imaging device, and controlling method

Pixel signals are sequentially output from an image sensor in a reverse order to an order in which light sensing cells are arranged with respect to one of a horizontal direction and a vertical direction. In an image processor, first, a data reading part transfers the pixel signals in the same order as corresponding light sensing cells are arranged with respect to both of a horizontal direction and a vertical direction, and a signal sequence of the pixel signals is changed. Then, the pixel signals which are output group by group are sequentially selected by a selector in accordance with a sequence of groups. As a result, the pixel signals can be supplied from the selector in an order conforming a two-dimensional array of the light sensing cells, to thereby facilitate color interpolation which is to be later performed by a color interpolator.

Image processor that controls transfer of pixel signals between an image sensor and a memory

RGB image data outputted from an ADC () is processed in an SPU () and an RPU () and then buffered into a memory () as YUV image data. The YUV image data is outputted from a YUV output unit (), encoded by an image compression and expansion chip (A) and transmitted to a main chip () by a DMAC (). On the other hand, compressed moving image data stored in the memory () is transmitted to the image compression and expansion chip (A) through the control by a DMAC (), decoded therein, then converted into RGB image data in an RGB sampling unit () and inputted to the main chip () by the SPU () through a data line (). With such a construction, it is possible to provide a circuit for compression and expansion, which allows connection with a main processing chip having no YUV input circuit without increasing circuit scale, maintaining general versatility of those circuits.

Image compression and expansion device

For an electronic apparatus in which data is transferred between a plurality of processing devices and a memory, a technique is provided which prevents the data transfer from being restricted and allows the processing devices to operate efficiently. The order of priorities of data transfer operations through channels is changed on the basis of a relation between thresholds and the amounts of data remaining respectively in FIFO buffers. This prevents the FIFO buffers from becoming empty of data, or from being filled up with data, which allows the devices to operate efficiently.

Memory control apparatus and memory control method

Color-difference signals that become unnecessary after rotation are deleted from a second pixel while saving color-difference signals that become necessary after rotation in the second pixel, to thereby form image data conforming to YUV422 format. The image data is then rotated, and subsequently the color-difference signals saved in the second pixel are returned to the original first pixel, to thereby form image data conforming to YUV422 format.

Image processing device

A sensor such as a CCD image pickup device is equipped with a color filter of RGB Bayer array. An image is read from such a sensor (S) and inputted to a color interpolation device as raw data (S). The color interpolation device calculates additional values DH and DV of differential absolute values of pixel values in a horizontal direction and a vertical direction by using pixels of all colors in a peripheral area of a specified pixel (Sand S). The additional values DH and DV are compared with each other (S) and when it is judged that there is a tendency of pixel drift in the horizontal direction or the vertical direction, Sis executed. In S, when a correlation in the vertical direction is strong, an interpolation using vertical adjacent pixels is performed and when a correlation in the horizontal direction is strong, an interpolation using horizontal adjacent pixels is performed. By this method, it is possible to improve the accuracy of color interpolation.

Color interpolation method in bayer array

An image conversion device is provided with a first buffer area for storing either one of even field and odd field of inputted dot sequential data and a second buffer area for storing the other thereof. A data transfer control circuit controls in such a manner that, during a period in which one of the two fields is written in the first buffer area, the other field, stored in the second buffer area, is read out in a color field sequential format, and during a period in which the other field is written in the second buffer area, the other field, stored in the first buffer area, is read out in a color field sequential format. A pixel interpolating circuit carries out an insertion-interpolating process on the field read out from the image storing unit, and outputs the resulting data. Thus, it becomes possible to prevent color breaking at the time of displaying motion images on a color field sequential type display by using a buffer area having a capacity of one frame.

Image conversion device, image conversion method and data conversion circuit as well as digital camera

A hybrid pixel interpolating apparatus () has a function of converting raw image data (D) having one color component for each pixel into pixel interpolated data in which each pixel has a plurality of color components. This hybrid pixel interpolating apparatus () includes: a register () for holding pixel data in a predetermined pixel region in the raw image data (D) to be inputted; a plurality of pixel interpolating parts ((n: integer not less than 2)) for sampling pixel data (D) inputted from the register () to execute a pixel interpolating process; and a mixing coefficient calculating part () for calculating mixing coefficients (&#x3b1;, &#x3b1;, . . . , &#x3b1;), and also includes a mixing part () for fetching and mixing interpolated data (DI, DI, . . . , DI) outputted from the respective pixel interpolating parts (to) to output the resultant. In the mixing coefficient calculating part (), the mixing coefficients (&#x3b1;to &#x3b1;) are calculated for each of the pixel interpolating parts (to) so as to suppress the deterioration in image quality at minimum.

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Osaka, Japan

Takashi Matsutani